The ZX97 is a discrete logic clone of the ZX81. It is functionally 
equivalent and 100% compatable but has numerous enhancements over 
the original ZX81. The all CMOS design draws only 50 mA and can 
be easily powered from a small battery. 
The total memory is increased from 9K to a 192K including 32K of 
EPROM and 160K of battery backed up SRAM. A SHADOW RAM feature  
allows users to enhance or replace the ZX81 operating system with 
the ZX80, FORTH or any other OS software. 
The 16 parallel bidirectional I/O lines are connected to an IBM 
compatable printer port (LPT1) and can also be used for high speed 
communication with a PC or for robotics applications. 
Aside from the existing ZX81 screen text and graphics, the ZX97 offers 
a full 128 upper and lowercase text characters and unlimited user defined 
graphics (UDG) And finally, the ZX97 supports both pseudo hires and true 
bitmapped graphics (192x256) programs. 
The ZX97 circuit is described in functional blocks as shown in FIG 1. 
and circuit details are shown in the schematic FIG 2. 

CRYSTAL TIMEBASE / MEMORY MAPPER CIRCUIT 
----------------------------------------- 
The circuit in Fig 2A generates the 6.5MHz video clock, the 3.25MHz 
CPU clock and the 15.75KHz horizontal clock. 
The 6.5 MHz crystal clock is divided by 2 with one stage of 74HC74 to 
generate the CPU clock. The 74HC393A dual 4 bit counter together with 
the 74HC11 divides the CPU clock further by 207 to generate the 15.75 KHz 
horizontal frequency. The 74HC08 generates 4.6 us wide HSYNC pulses 
which are gated by the VSYNC and NMI latches before routing to the 
video/sync mixer and the CPU NMI input. The counter is also held reset 
during the VSYNC period to maintain synchronization between the software 
generated VSYNC and the hardware generated HSYNC (in the FAST MODE). 

MEMORY MAPPER 
A novel memory decoder using a 74HC251 generates the memory chip select 
signals. ZX97 system memory map is as follows: 0-8K EPROM or SHADOW RAM, 
8-40K system RAM, 40-48K EPROM (extended OS) and 48-64K bank switched 
EPROM/RAM DISK memory. The memory segment 32-40K is used as system RAM or 
can be mapped over the 0-8K area to install and test a modified BASIC 
or other operating system by closing SW1. In that case the 0-8K RAM is 
write protected and the 0-8K EPROM segment is remapped to 32-40K. Note 
that the 74HC251 is enabled with MREQ or RFSH to access the video pattern 
data. The RAMDISK is also enabled by the ROMCS signal but the DISKON signal 
disables the EPROM /OE and enables the RAMDISK CE in the 48-64K area. 

ZX97 CPU/SYSTEM MEMORY 
---------------------- 
The ZX97 uses a CMOS Z80A CPU for reduced power consumption. 
Details of the Z80 can be found in the ZILOG literature. 
Fig 2b show the RAM and EPROM chips which are also low power CMOS. 
Parts of the video circuit which address the memory at REFRESH time 
includes the CHR$ latch which generates part of the pattern table 
address from the CHR$ code. The 3 bit LCNTR is incremented with HSYNC 
and generates the pattern table 3 LSB address bits. The CPU I register 
generates the pattern table base address. Additional circuits disable 
the pattern table address circuit when A14 is high for TRUE HIRES programs. 
Loading an odd byte value into the I register enables the expanded pattern 
table offering 128 unique character pattern shapes. 

SYSTEM RAM and EPROM 

Both system RAM and EPROM are 32K byte CMOS devices. The RAM is battery 
backed up and write protected in the 0-8K segment to avoid corrupting the 
shadow RAM data from spurious writes when switched to the 0-8K segment. 
The EPROM will be changed in a future revision to a 128K byte device 
providing 64K of EPROM DISK and 64K of paged OPERATING SYSTEM code. 

ROW COUNTER / CHR$ LATCH 

The Sinclair text mode is supported with a pattern table in EPROM at address 
1E00-1FFF. User Defined Graphics (UDG) RAM pattern tables are also supported. 
UDGs are accessed by changing the I register to point to the new pattern 
tables in RAM or EPROM which must be located in 0-16K or 32-48K. One half 
of a 74HC393 dual hex counter is used as a modulo 8 line counter which 
increments every HSYNC pulse and during RFSH time it addresses the 8 lines 
of patterns for each character. The line counter is reset with VSYNC. 
The 74HC374 CHR$ latch is loaded with each DFILE character code and during 
RFSH it is used to address the corresponding pattern table entries. 
Two bits of the 374 and a 74HC125 are used to provide tristate outputs for 
the line counter. 

ZX97 RAM / EPROM DISK 
--------------------- 
Fig 2c  shows the simple circuit requirements to provide 128K of RAM DISK. 
The RAM DISK is accessed at 48-64K (C000-FFFF) in 8 pages of 16K each using 
the 8255 Port PB0-2.  PB3 is used with A14-15 to select 8 pages of RAMDISK 
or one page of EPROM disk. PB4 is used for write protection and a manual write 
protect switch is also included. A RAMDOS program is included in EPROM which 
makes it easy to save and load program, variable and binary files. 

ZX97 VIDEO LOGIC 
---------------- 
In the Sinclair video system, the CPU is a key element in the display 
circuit. Most other PC's use a separate video controller with video memory 
access multiplexed between the CPU and the video controller. 
In the ZX81/97, the CPU is multitasking between application program 
and display file execution. During video task excecution, the Z80 is used 
to sequentially read character codes from the "screen memory" which is a 
segment of system RAM pointed to by the system variable DFILE. 
Then the CPU, together with the linecounter and CHR$ ragister, generates the 
pointer to the pattern byte which is loaded into the video shift register 
and clocked out as a video bit stream. During true high resolution graphics 
mode, the CPU does all the work, pointing directly to the bit mapped patterns 
in a 6K hires display file which are sequentially loadind into the video 
shift register. For more detailed information, see the ZX81 Video Tutorial. 

THE NOP LOGIC 

An important element in the video circuit is decoding access to the DFILE. 
When a valid CHR$ code is read from the video display (DFILE) , the NOP LOGIC 
(74HC138) and a 74HC08 AND gate decodes this condition. The NOP LOGIC output 
turns on a 74HC245 buffer to "force" a low level on the CPU data bus thereby 
tricking the Z80 into executing NOPs during DFILE execution. 

VIDEO SHIFT REGISTER/VIDEO INVERT LOGIC/VIDEO SYNC MIXER 

The NOP LOGIC is used to generate the video shift register load signal 
if a valid CHR$ is read from DFILE. Since this occurs at the end of the 
"forced" NOP, the NOP LOGIC output is saved in the NOP register (74HC74A) 
on the rising edge of RD. The NOP register is clocked into the S/L register 
(74HC74B) on the rising edge of the T1 decoder (74HC08). Feedback to the SET 
input of the NOP register resets the S/L register after a 30 nsec gate delay. 
This generates a 30 ns pulse to load the pattern byte into the video shift 
register. The D7 bit of the CHR$ code is saved in the D7 register (74HC74A) 
on the rising edge of RD and is clocked into the INVERT register (74HC74B) on 
the rising edge of the LOAD PULSE at the same time as the pattern byte is 
loaded into the video shift register. 
The video shift register is loaded with the video pattern data from RAM 
or EPROM, the pixels are clocked out at 6.5 MHz and the pixels are inverted 
with a 74HC86 if the INVERT register bit is set. 
The output from the 74HC86 XOR gate is passed through a 74HC74 video  
synchronizer flip flop eliminating any effects of differential time delays 
between the VIDEO input and the INVERT inputs of the XOR gate.         
The CSYNC signal is conected to the serial input of the shift register to 
produce a black level (back porch) after each sync pulse. 
The video is combined (mixed) with the CSYNC signal to produce a composite 
video signal suitable for connecting to a video monitor or RF modulator. 

ZX97 GRAPHICS 

New pattern tables in 32-40K RAM  can be used to enhance the normal 
Sinclair text mode. A new "extended" Sinclair text mode has been added 
which provides 128 unique character patterns (ie upper and lower case). 
In the ZX97, the video pattern tables are located in both EPROM and RAM 
(unlike the ZX81) providing user definable character (UDG) sets. 
Pattern data is read during RFSH with the I register and the ROW counter/ 
CHR$ latch hardware. 

Both true hires software based on WRX16 and HRG algorithms and the 
"pseudo" hires programs like Rock Crush are supported by the ZX97. 

True High Resolution graphics programs (ie WRX16) fetch pattern data 
from system RAM using the I and R registers and the pattern table lookup 
hardware has to be disabled.  A high on A13 or A14 is used to disable  
the ROW counter/CHR$ latch tristate outputs during RFSH. 
The memory map for Sinclair character and pseudo hires patterns is 0-8K. 
For UDG and 128 character text, pattern data must be located in 32-40K. 
All other parts of the memory map are true hires.  

Pseudo Hires is supported without any changes to provide downward 
compatability with many excelent programs such as Rock Crush. 
For future software development, UDG's and True Hires would appear 
more logical choices, given the new ZX97 hardware features. 

ZX97 I/O CIRCUIT 
---------------- 
The ZX97 I/O circuit in Fig 2e includes the keyboard logic, TAPE IN/OUT 
logic, part of the SYNC/NMI logic which is I/O mapped and the 8255 logic. 
To maintain compatability with the ZX81 I/O port assignment, the same 
incomplete I/O address decoding is used for I/O address bits 0-3. 
A few 74HC32 OR gates provide the necesary logic to access the NMI and 
SYNC latches. A more conventional I/O decoding circuit is used to 
generate address DF for the 8255 24 bit parallel interface controller. 

KEYBOARD LOGIC 

The ZX97 keyboard interface uses the same A8-15 row scanning as the ZX81 
and the five keyboard data lines are connected to bits D0-4 of a 74LS245 
tristate buffer. The output is enabled with IN FE to read keyboard colunm 
data. Two other bits (D6-7) are used to sense the 50/60 Hz option and the 
TAPE input. 

THE TAPE INPUT/OUTPUT 

The TAPE INPUT is compatable with ZX81 as well as the ZXTAPE system for 
PC<>ZX data transfer using a simple 2 wire cable connected to the PC 
printerport. Data is saved and loaded with the build in functions. 
The "easy to use" ZXTAPE.EXE program takes care of the PC hardware. 
The TAPE OUT signal (actually the VSYNC) is a TTL level suitable for 
line in of a tape recorder and is also connected to STATUS input of 
the LPT1 connector. 

NMI AND VSYNC LATCHES 

Two SR latches are used to control the flow of NMI pulses to the CPU and 
SYNC pulses to the VIDEO/SYNC MIXER. The NMI latch is set with OUT FE 
which gates the NMI pulses to the CPU and is reset with OUT FD. 
The NMI latch, when off, also enable the set input of the VSYNC latch. 
The action of the SYNC latch is a little more complicated because it 
produces a VSYNC pulse which is XOR'd with the HSYNC pulses to generate 
a negative sync level for as long as the VSYNC latch is set. 
The SYNC latch, which is set with IN FE, also resets the 15.75 KHz counter 
to maintain synchronization between the VSYNC and HSYNC in the FAST mode. 
The XOR gate inverts the inactive HSYNC output and thereby generates the 
negative vertical VSYNC pulse. Any OUT command resets the VSYNC latch, 
terminates the VSYNC pulse and enables normal HSYNC pulses. 

8255 PARALLEL I/O PORT 

The 8255 is a general purpose parallel I/O port. The 8255 defaults to 
3 input ports on reset and to configure ports for output, a control word 
must be written to the control register located at address DF. 
Port A is generally used as a high speed interface to a PC printer port. 
Port B is used for control of the RAM disk and Port C is used for hand 
shaking with the PC printer port. Ofcourse Port A and C can be used for 
any general purpose parallel I/O. 

The 8255 is accessed at I/O address DF and the internal registers are 
addressed with A3 and A4. Therefore the control register is at port DF 
and the data registers for ports A to C are addressed at C7, CF and D7. 

Note: Port C output bits can be accessed at two different locations. 
Port C output byte is accessed at D7, but in addition, individual 
Port C bits can be set or reset at address DF with control word values 
00 to 0F. Even values 02 to 0E reset bits 0 to 7 respectively and odd 
values 01 to 0F set bits 0 to 7. 
 

With questions I can be contacted by email 

This homepage is best viewed with Netscape.               Last update 19-04-99