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'ZEL' electronics

little home page

last modify 21.december 1999.

 

This page is built for fast information about our work, and we represent our:

 

IDE controller principals

 

Contents:

1. Initial idea & introduction

2. IDE connections

3. IDE adressing

4. Register description

5. IDE Commands and command cycle

6. 8255 <=> IDE

7. Summary

8. About us

 

........1. Initial idea and introduction:

Our first idea was to connect IDE disk to some microcontroller (exactly Atmel's 89C52 what we using).First step was to find datasheets about IDE.On the internet you can find much of that, but all of this is very detailed (like ata3-r6.doc, very detailed desription, but this text have 185 pages with much of details what we dont need), or very small texts (like some non-finished project to connect LPT => 8255 => IDE with schematic and some Pascal source with autor's appendix that this project never works, and dont ask him why???).

Note: Our text will no explain some things like 'What is cylinder?' or 'What is Master?'.

Anyway, in this moment we have this:

........2. IDE connections:

To make this controller, we dont use ALL IDE pins, so this description is only for used pins.

This is:

1........../RESET

25......../RD

23......../WR

38......../CS0

37......../CS1

36........A2

33........A1

35........A0

17,15,13,11,9,7,5,3......D0..D7 (lo byte for data transfers)

4,6,8,10,12,14,16,18......D8..D15 (hi byte for data transfers), for both data bytes numbering is in presented in order from LSb to MSb.

2,19,22,24,26,30,40.............GROUND

39......../ACTIVE - useful for LED - activity indicator.

 

........3. IDE adressing:

IDE disk is adressed by signals: /CS0,/CS1,A0,A1 and A2 in following combinations (for classic CHS notification):

/CS0 /CS1 A0 A1 A2 DESCRIPTION
0 1 0 0 0 16 bit register for all data transfers
0 1 0 1 0 sector counter register (No. of sectors to read/write).In small systems like microcontrollers always 0x01
0 1 0 1 1 No. of first sector to read/write.On IDE interface sector counter counts from 1 (not from 0)
0 1 1 0 0 lo byte of cylinder number
0 1 1 0 1 hi two bits of cylinder number
0 1 1 1 0 head and dev. select.Bit 7-5 is 101 for CHS,bit 4 is 0 for master, 1 for slave, bits 3-0 is head number
0 1 1 1 1 device status register - it is for command writing, or status reading
1 0 1 1 0 second status register - used for software reset and to enable/disable interrupts

Note: only first register in the table is 16 bit, all other are 8 bit.

This description is useful for C(ylinder)H(ead)S(ector) positioning on HD space.This is useful for small,old disks.For this we have not interest.Our interest are LBA disks (greather than 500 MB).

Detailed differences between CHS and LBA we will not present.

Most important differences are:

/CS0 /CS1 A0 A1 A2 DESCRIPTION
0 1 0 1 1 lowest byte of LBA sector
0 1 1 0 0 lo byte of LBA sector
0 1 1 0 1 hi byte of LBA sector
0 1 1 1 0 head and dev. select.Bit 7-5 is 111 for LBA,bit 4 is 0 for master, 1 for slave, bits 3-0 is highest 4 bits of LBA sector
0 1 1 1 1 device status register - it is for command writing, or status reading
1 0 1 1 0 second status register - used for software reset and to enable/disable interrupts

LBA sector numbering comes from sector1 to max.

Sector is smallest data unit on IDE disk, and it have 512 bytes.So, for any data reading/writing from/to disk, we have 512 bytes of data.If you want to read exactly one byte from disk, you must read all 512 bytes (one sector where is your data byte) and find out your byte.

Number of sectors on IDE disk is (sectors per track)*(number of tracks)*(number of heads).

 

 

........4. Register desription:

Upper two tables telling everything about registers except about two status registers.

Most important bits in device status register:

3 - DRQ........This bit is 1 after disk response write command.It indicates that disk need data to write (256 words - one sector).

6 - RDY........This bit is 1 when hard reset is finished.

7 - BSY........This bit is 1 when disk is busy.You must wait to be 0 before any command.

Most important bits in secondary status register:

1 - Write 0 to this bit to enable IRQ, disable IRQ when is 1.IRQ comes on pin 31 on connector after execution of command.We dont use IRQ, so always is 1.

2 - After writing 1 to this bit software interrupt will be executed.Must write 0 in it after BSY go to 0.

Note: This is MOST important bites in this registers.Must write 00000010 to secondary status reg. for default.

Here is NO explanation for error control.

Note2: any reading/writing to registers you must do by this way:

- set /CS0,/CS1,A0,A1,A2 adress on IDE

- give the /READ or /WRITE signal.

 

........5. IDE Commands and command cycle:

0x20 - Read. After recognizing this command, IDE will fill 256-word fifo buffer.You have just to read it.Before writing this command to status register,you must write full LBA sector number to sector,cyl.lo, cyl.hi, head registers.

0x30 - Write. After recognizing this command, IDE set DRQ and wait to fill his 256-word fifo buffer.You have just to write 256 words to it from first to last.Before writing this command to status register,you must write full LBA sector number to sector,cyl.lo, cyl.hi, head registers.

0xEC - Drive data. After recognizing this command (without any parameters), IDE will fill 256-word fifo buffer.You have just to read it.There you have very useful data like serial number, manufacturer,model, cyls,heads,sec/track, number of LBA sectors (if disk is LBA).

Note: This is three most important commands, without error control.

Command cycle:

First thing is to check RDY bit in status register.

1. Read

- wait to busy bit in status register go to 0,

- fill the LBA number to registers sector,cyl.lo, cyl.hi, head,

- write the READ command to status register

- wait to DRQ bit in status register go to 1,

- sequentially read 256 words from buffer true data register.

 

1. Write

- wait to busy bit in status register go to 0,

- fill the LBA number to registers sector,cyl.lo, cyl.hi, head,

- write the WRITE command to status register

- wait to DRQ bit in status register go to 1,

- sequentially write 256 words to buffer true data register.

This is it.

 

 

........6. 8255 to IDE:

First simple idea was to connect 8255 to IDE by this way:

8255 IDE
PA /RST , /RD , /WR , /CS1 , /CS0 , A2 , A1 , A0 (connected by this way from PA7 to PA0
PB D0-D7
PC D8-D15

but, there was some little problem.

For 8255 in this application you have two configurations: 0x8B (PA out, PB in, PC in) and 0x80 (all out).

When you switch 8255 from/to this two configurations, all output ports come to 0x00. That have effect to hardware resetting disk, or some undefined condition.

We invert this five signals (/RST , /RD , /WR , /CS1 and /CS0) by one 7404 and problem is solved.

 

 

........7. Summary:

We connect this 8255 to one Atmel's 89C52 what communicate with terminal by serial port. All commands work fine (read sector, read group of sectors, also write).

Our initial idea is finished and we have working prototype. In this moment primary for us is JUST to read DOS filesystem (in FAT32) to observe how this thing work. After that, writing is not big problem.Also, we want to connect ATAPI CD rom to our controller, make autorecognize disk parameters .......

This text is very fast and short information about our work, and we make this page to have easy answer to people who want to do something like this.

 

 

........8. About us:

We are Zlatko Kursar and Zeljko Vincic.Our small company 'ZEL electronics' is placed in Pula, Croatia.Our job is electronics, automatics, software for POS systems and audio equipment.

All summer we spend on the sea trying to learn english, like you can see in this page.

We recommend to visit Bascom Pool if you programming 8051's and so.

Send us a e-mail, or tel/fax : +385 52 21 03 09.

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