This section discusses the data subsystem of the LM (as it is found in the LM's handbook), that is the system which allows to collect all the informations of the LEM, and format them into a train of digital informations (DATA PCM) which can be transmitted to the CM or the earth, and also recorded.
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I'll first open the ball with the resistance-to-dc converters;
They say their output is linear with temperature changes which obey the following table.
If I compute the variation of resistance for a variation of temperature of one degree, I find the following values for the five first entries of the table:
3.07, 3.06, 3.05, 3.12, and 3.12 ohms per degree; the difference between these values is less than 0.1 ohm.
But for the last entry of the table, I find 4.46 ohm/degree, which makes almost 1.5 of difference with the previous values, which is really much, considered that the previous values are all much closer to each other.
So, why so much difference for the last value?
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In this analog multiplexer gate driver, they say that a row driver is switched on by a positive-going row command from the programmer; that means that the row driver is set to high a when the programmer's row command is activated, and remains high even when the programmer's row command is disactivated; so my question is: How is the row driver switched off, if the programmer's command can only switch it on?
And it's the same thing for a column driver.
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This schema shows the high-level analog gates which allow the selection of inputs according to the values of the matrix command.
The outputs (PAM) are validated when the corresponding row(s)/column(s) are activated, and disactivated otherwise.
We first can see on Block A that a control input of a HLAG is an AND of five columns of the matrix command.
It was not necessary to have that many columns ANDed; if the columns A1 and A2 also have another use, the columns A3, A4, and A5 are only used in this AND gate, so they are redundant.
We here have a redundancy of inputs.
And on block B, we can see that the columns B1, B2 and B3 are used as outputs to be used as column inputs to another card, but an AND of these columns is also purposed to be used as a column input to this card; this is useless, for the AND of these columns bears no new information relatively to these columns.
We here have a redundancy of outputs.
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In the first block there are Two HLAGs (High-Level analog gate) I have circled.
Each HLAG has:
. One input
. One output
. And two control inputs (Row/Column) which either allow the output to copy the input, or disable it.
So, let's see the connections of these HLAGS:
The bottom HLAG:
- has an Input (Input A1, coming from the SCEA) that I have colored in green.
- has a Row control input (Row A) that I have colored in orange.
- has a column input (Column A1) that I have colored in red.
- and has an output that I have colored in pink, and which is an input to the top HLAG.
The Top HLAG:
- Has an input which is the output of the bottom HLAG.
- has a Row control input (Row A) that I have colored in Orange.
- Has a Column input which is the AND of the columns A1, A2, A3, A4 and A5 of the matrix command.
- And finally has an output which is final output of the block, that is the First PAM output.
Now, why does not this make sense?
For the top HLAG's output to be validated, its column input has to be activated; but this column input is an AND of the columns A1, A2, A3, A4 and A5, and will only be activated if all these columns are activated; in particular if A1 is not activated, the Top HLAG's control input will not be activated, and the HLAG's output will be disactivated.
So, for the Top HLAG to be validated, Row A and column A1 (along with columns A2,A3,A4 and A5) have to be activated, but, if Row A and column A1 are activated, then the bottom HLAG is also validated.
So the bottom HLAG is completely useless, the input of this circuit could directly have been connected to the input of the top HLAG, it would have given exactly the same result!
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the block B has three HLAG that I have circled.
The first HLAG (the top one):
- Has an input (Input B1, coming from the SCEA), that I have colored in green.
- Has a Row control input (Row B) that I have colored in orange.
- Has a Column control input (Column B1) that I have colored in red.
- Has an output that I have colored in blue.
The second HLAG (the middle one):
- Has an input (Input B2) that I have colored in green.
- Has a Row control input (Row B) that I have colored in orange.
- Has a Column control input (Column B2) that I have colored in red.
- Has an output that I have colored in blue.
The third HLAG (the bottom one):
- Has a Row control input (Row B) that I have colored in orange.
- Has a Column control input (Column B3) that I have colored in red.
- Has an output that I have colored in blue, and which is common to the outputs of the two other HLAG!!
- So, the fourth connection can only be the input of the HLAG, there is no other possibility!
But, this input is not indicated as an input like it should be, it is indicated as an output, and even as the output of the block, the second PAM!
It is totally incoherent!
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The outputs of the high-level analog gates go to the High-Speed gates.
The outputs of the High-speed gates are connected together to be converted to digital.
This of course supposes that the inputs are validated alternately, it could not work if they were validated in the same time.
But the question is: What is the use of these High-Speed gates, since the high-level gates already make the alternate selection of signals?
The answer that they give is that these gates sharply cut the outputs of the high-level analog gates which would have a little lagging time.
It is in fact useless, for the High-Level PAM output is sampled by charging a capacitor during 39 microseconds, which is enough to absorb the effect of this lagging time.
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The analog PAM output is then converted to digital by an Analog-To-Digital circuit, of which the LM's handbook gives the following schema.
An Analog-To-Digital converter is a circuit which allows to convert an analog signal (which varies continuously) to its equivalent binary representation.
This circuit is used in hybrid calculators in which an analog computer (which works with analog signals) exchanges informations with a digital calculator (which works with binary informations).
Likewise, there is also a circuit (DAC) which allows to convert a binary word to its equivalent analog signal.
Wikipedia gives the following schema for an ADC (Analog-To-Digital converter).
This circuit works the following way:
A counter counts from an input clock: the binary outputs of the counter represent a digital word which progressively grows from 0 to the maximal value of the counter (and which represents the maximum value of the analog signal).
The outputs of the counter are inputs to a circuit (called Digital-To-Analog Conv on the Wikipedia's schema) which allows to convert the current outputs of the counter to an equivalent analog signal.
This converter is in fact a network of resistors of different values.
The most significant bit is connected to the resistor of the lowest value, because it must produce the highest current.
The resistor of the next bit has a resistor of the double value, and so on: the resistor connected to each bit has a value double of the resistor connected to the bit of the next higher weight.
The least significant bit is connected to the resistor of the highest value, because it must produce the smallest current.
(In the example shown, each resistor's value is not exactly exactly the double of the one of the previous resistor, because of the restriction of possible values of resistors).
The analog input to convert and the output of the network of resistors which give the analog equivalent of the counter are fed into a comparator which compares them.
As long as the equivalent analog output of the counter is below the analog input, the comparator allows the counter to count up.
When the equivalent analog output of the counter reaches the analog input, the comparator's output changes and blocks the counting of the counter (by forcing to zero the AND gate that the clock input goes through).
The comparator's output now signals that the counter holds a valid binary representation which corresponds to the analog input; the conversion is completed.
A signal allows to reset the counter (to make it count from zero) and also allows or disables the counting.
This simplified representation, with only four bits, shows, with an analog input which is half its maximum value, how the counter counts up to half its maximum value, and then the comparator's output changes, latching the current value of the counter which then holds the equivalent binary representation of the analog input (and also resets the counter).
These explanations were a little long, but I think necessary to well understand why the ADC which is shown in the LM's handbook is absurd.
In fact the representation of Wikipedia is simplified not to complicate too much the explanation of the circuit.
In reality, the outputs of the counter are latched when the comparator's output changes, so that the latched outputs constantly hold the binary equivalent of the analog input.
On this new schema (that I also found on internet), when the comparator's output indicates that the counter has not still reached the analog input, the Up control input of the counter is activated and its Down control input is disactivated, which means that the counter counts up; when the counter reaches the analog input, the comparator's output changes: the comparator's change triggers the latches which then take the values of the counter's outputs which currently represent the equivalent binary representation of the analog input; the Up control input of the counter is disactivated, stopping the up counting of the counter.
Conversely, if the current output of the counter corresponds to an analog value which is higher than the analog input, the comparator's output validates the Down control input of the counter and disactivates the Up control input, which makes that the counter counts down instead; when the counter's value reaches the analog input, the comparator's output changes and the current counter's values are latched again to be given as the current binary representation of the analog input on the latches.
With this ameliorated circuit:
- The outputs of the converter constantly hold the binary representation of the analog input
- The converter follows very fast small variations of the analog input, for it doesn't have to count from zero at each conversion cycle, but from the current value instead.
There is a little delay between the current analog input's value and the converted binary value, but, the higher the frequency of the clock signal, and the smaller this delay.
There is another way of making analog to digital conversion which is called "successive approximation A/D conversion".
I show on this diagram how a successive approximation A/D conversion register works.
The most significant bit of the SA register starts from 1, with the other bits set to 0; it represents in fact half the maximum value; then according to the comparator's value, the most significant bit is left to 1 (if the output of the DAC is greater than the analog input) or set to 0 in the converse case.
Then, at the next clock pulse, the next less significant bit is processed with the same treatment, and so on till the least significant bit is reached.
In 8 clock pulses, the SA register detains the binary representation of the analog input.
This type of converter is more efficient than a converter using a counter which counts exclusively up.
However, a converter using a counter which can count alternatively up and down can sometimes be still more efficient in case that the analog input has small variations.
Before describing how the successive approximation A/D works, I am going to have a word about the component it uses.
A flip-flop is a circuit with two inputs and an ouput:
- When the set input (left input) receives a positive edge, the output of the flip-flop is forced to 1.
- When the reset input (right input) receives a positive edge, the output of the flip-flop is forced to 0.
Outside these two cases, the output of the flip-flop does not change.
An AND gate is a simple circuit which has two inputs and one output, and its output is 1 only if its two inputs are also 1.
In all the other cases (i.e. the two inputs are 0, or only one input is 1), its output will be 0.
An OR gate works in a converse way: Its output is 0 only if its two inputs are 0; in all the other cases (i.e. the two inputs are 1, or only one input is 1), its output will be 1.
A differentiator is a circuit which subtracts to the voltage which goes into its '+' input the voltage which goes into its '-' input; the result of this subtraction is on its output.
Consequently, the output of the differentiator will be a positive voltage if the voltage on its '+' input is greater than the voltage on its '-' input, and a negative voltage in the converse case.
It is easy to convert the positive voltage to a 1 (or to a 0) and the negative voltage to a 0 (or a 1).
The differentiator then plays the role of a comparator of voltages and can provide a binary information which allows to test one voltage relatively to the other one.
I'll make a simplified demonstration of the way the AD converter works on 4 bits.
The differentiator is simplified so it directly outputs a 1 if the analog conversion of the binary information is greater than the analog input to convert, and 0 in the converse case (i.e. less than or equal to).
For more clarity, I'll draw the lines in a high state (1) in green and the lines in a low state (0) in red.
In the schema I show I'll use the following convention:
When two lines cross each other, they have no electrical contact between eath other, unless I put a full circle on their intersection.
However, if one line ends on another one, I'll consider there is a contact between the two, without the need of putting a full circle on their common point.
I'll make a first demonstration with a voltage 0.625V on the analog input (V representing the maximum value).
The timing generator initially triggers it leftmost line (it triggers them successively from the left to the right).
This line goes into the set input of the leftmost flip-flop (which corresponds to the most significant bit of the conversion).
Consequently the output of this flip-flop is set to 1.
This line also goes into OR gates of which the outputs go to the Reset inputs of the other flip-flops; consequently these OR gates output a 1 which allows to reset the corresponding flip-flop.
After having triggered this line, the timing generator has set the first bit of the conversion to a 1 and the other bits to 0, which corresponds to a voltage of 0.5V ont the output of the net of resistors.
This voltage is less than the voltage of the analog input, and the output of the comparator is consequently set to 0.
Then the timing generator triggers its second line (starting from the left).
This line goes into the first AND gate of which the other input comes from the differentiator; as the output of the differentiator is currently 0, the output of this AND is also 0; the output of the OR it is connected to is also 0, for the first line of the TG is currently 0; so the Reset input of the first flip-flop remains to 0, and the flip-flop is not reset; its output remains to 1.
The second line of the TG also goes into the set input of the second flip-flop, and the output of this one is consequently set to 1.
We now have the configuration "1100" on the converted bits which corresponds to a voltage of 0.75V on the output of the net of resistors; this voltage is greater than the analog input, and consequently the output of the differentiator is set to 1.
The timing generator now triggers its third line; this line goes into the second AND gate of which the other input comes from the differentiator; as the output of the differentiator is currently 1, the output of the AND goes to 1, and the output of the OR this AND is connected to is also forced to a 1; consequently the second flip-flop is reset and its output goes to 0.
The third line of the TG also goes into the set intput of the third flip-flop of which the output is forced to a 1.
We now have the configuration "1010" on the converted bits which corresponds to a voltage of 0.625V equal to the analog input.
The output of the differentiator is set to 0.
The timing generator now triggers its fourth line; this line goes into the third AND gate of which the other input comes from the differentiator; as the output of the differentiator is currently 0, the output of the AND remains to 0, and so does the output of the OR it is connected to; consequently the third flip-flop is not reset, and its output remains to 1.
The fourth line of the TG also goes into the set input of the fourth flip-flop of which the output is forced to a 1.
We now have the configuration "1011" on the converted bits which corresponds to a voltage of 0.6875V greater than the voltage of the analog input; consequently the output of the differentiator is set to 1.
The timing generator now triggers its fifth line; this line goes into the fourth AND gate of which the other input comes from the differentiator; as the output of the differentiator is currently 1, the output of the AND is set to a 1, and the output of the OR it is connected to is also set to 1 thus forcing the reset of the fourth flip-flop; the output of this one thence reverts back to 0.
The conversion is over, and the outputs of the flip-flops hold the converted value of the analog input, that is "1010".
I now make a second demonstration with a voltage 0.3125V on the analog input.
The timing generator initially triggers it leftmost line.
This line goes into the set input of the leftmost flip-flop.
Consequently the output of this flip-flop is set to 1.
This line also goes into OR gates of which the outputs go to the Reset inputs of the other flip-flops; consequently these OR gates output a 1 which allows to reset the corresponding flip-flop.
After having triggered this line, the timing generator has set the first bit of the conversion to a 1 and the other bits to 0, which corresponds to a voltage of 0.5V on the output of the net of resistors.
This voltage is greater than the voltage of the analog input, and the output of the comparator is consequently set to 1.
Then the timing generator triggers its second line (starting from the left).
This line goes into the first AND gate of which the other input comes from the differentiator; as the output of the differentiator is currently 1, the output of this AND is set to 1; the output of the OR it is connected to is also set to 1, so that the first flip-flop is reset and its output goes to 0.
The second line of the TG also goes into the set input of the second flip-flop, and the output of this one is consequently set to 1.
We now have the configuration "0100" on the converted bits which corresponds to a voltage of 0.25V on the output of the net of resistors; this voltage is less than the analog input, and consequently the output of the differentiator is set to 0.
The timing generator now triggers its third line; this line goes into the second AND gate of which the other input comes from the differentiator; as the output of the differentiator is currently 0, the output of the AND remains to 0, and the output of the OR this AND is connected also remains to 0; consequently the second flip-flop is not reset and its output remains to 1.
The third line of the TG also goes into the set intput of the third flip-flop of which the output is forced to a 1.
We now have the configuration "0110" on the converted bits which corresponds to a voltage of 0.375V greater than the analog input.
The output of the differentiator is consequently set to 1.
The timing generator now triggers its fourth line; this line goes into the third AND gate of which the other input comes from the differentiator; as the output of the differentiator is currently 1, the output of the AND is set to 1, and so is the output of the OR it is connected to; consequently the third flip-flop is reset, and its output changes to 0.
The fourth line of the TG also goes into the set input of the fourth flip-flop of which the output is forced to a 1.
We now have the configuration "0101" on the converted bits which corresponds to a voltage of 0.3125V equal to the voltage of the analog input; consequently the output of the differentiator is set to 0.
The timing generator now triggers its fifth line; this line goes into the fourth AND gate of which the other input comes from the differentiator; as the output of the differentiator is currently 0, the output of the AND remains to 0, and so does the the output of the OR it is connected to; the fourth flip-flop is not reset, and its output remains to 1.
The conversion is over, and the outputs of the flip-flops hold the converted value of the analog input, that is "0101".
So these demonstrations have allowed to show how the AD converter of Apollo was supposed to work.
So, what's wrong with this AD converter which seems to have all the components of a normal successive approximation converter?
First there is the output of an OR gate which is indicated as an input to this gate and not an output like it should be.
I have corrected the direction of this output on this schema.
Then there is an imaginary output (or input?) of a flip-flop which is connected to the output of the net of resistors through a resistor; in fact this output does not exist (and if it was the +5V or the ground the flip-flop is connected to, it would make the output of the net of resistors invalid).
I have removed this resistor which has no reason to exist on this schema.
Then we now have a much more embarrassing error, one in fact which makes that this converter cannot work.
Instead of being connected to the differentiator as two different inputs, the output of the net of resistors and the analog input to convert are connected together as a single input to the differentiator, and the second input of the differentiator is not connected at all.
It has no chance to work: The differentiator will not allow to compare the output of the net of resistors with the analog input the way it is connected.
I have corrected the converter so that the output of the net of resistors goes to an input of the differentiator and the analog input to convert goes to the other input of the differentiator.
Why can't it work if the analog input to convert and the ouput of the DAC (net of resistors) are directly connected together?
On this schema, I show the analog input connected to the net of resistors through a resistor, both being connected to first input of the differentiator, and the second input of the differentiator being connected to a reference voltage.
The higher the voltage of the analog input, and the lower the configuration of the converted bits to make the first input of the differentiator match with the reference voltage, and conversely, the lower the voltage of the analog input, and the higher the configuration of the bits to make the first input of the differentiator match with the reference voltage.
So this connection would make that the converted bits would be some sort of complement of the analog input relatively to some reference voltage, and not at all the conversion of the analog input.
Anyway, it does not even work this way, for the second input of the differentiator is not connected at all!
It simply cannot work; the only way which works is to connect the analog input on one input of the differentiator and the output of the net of resistors on its second input.
Then the timing generator sends query pulses to interrogate the output of the differentiator; but it does not have to do that, for only the timing generator can change the output of the differentiator by triggering one of its lines, so why would it try to query the output of the differentiator meanwhile?
I have removed the useless line from the timing generator sending irrelevant query pulses.
Finally the outputs of the AD converter are indicated as the outputs of the AND gates.
But the real outputs of the AD converter are not the outputs of these gates but the outputs of the flip-flops.
The outputs of the AND gates are all zeroes at the end of the conversion, for the lines of the timing generator are currently at a low state.
I have corrected the schema to show which are the real outputs of the AD converter.
Anyway it does not change much, for the outputs of the flip-flops do not hold a valid conversion either, given the wrong way the differentiator is connected.
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This is the diagram of the programmer.
The programmer is in some sort the orchestrator; it manages the serialization of the train of informations, and controls the matrix of signals (Rows/Controls) which allow to select the information which is currently serialized.
The informations are converted to digital and sent one after another in a train of informations which follow each other, and are alternately selected by the programmer.
This train of informations (DATA PCM) is then modulated and transmitted to the CM or the earth (MSFN).
It can also be recorded (by the DSEA).
It can be serialized according two different bit rates: A fast one, 51200 bits per second, and a slow one, 1600 bits per second.
You can see that there is a big difference between these two bit rates, for the first one is 32 times faster than the second one!
In the normal (fast) mode, the frames are organized in subframes which each contain 50 prime frames.
Each prime frame is constituted of 128 8-bit words; the first four words of a prime frame is a synchronization group.
The fourth word of the synchronization group is a Frame's ID which counts from 1 to 50.
It comes from a counter, and it is also used for the selection of the digital multiplexer gates in order to send into the prime frame the corresponding information.
The third word contains the current mode (normal mode).
And the second word is used for requesting the change from normal (fast) to reduced mode.
Each bit is sent in 1/51200=0.0000195 second.
Each word (8 bits) is sent in 8/51200=0.000156 second.
Each prime frame (128 words) is sent in (128*8)/51200)=0.02 second (20 milliseconds)
And each subframe is sent in (50*128*8)/51200=1 second.
So a subframe is sent each second in normal mode.
You would think that in reduced (slow) mode, the subframes are constituted the same but sent 32 times slower.
Not at all: In the reduced mode, a subframe contains only one unique prime frame of 200 words, and is also sent in one second.
The prime frame also contains a synchronization group, but the counter of the fourth word always contains 1, for there is only one prime frame; so it is not necessary, and could have been used to send information instead; it is also used in case of bit rate change, but the bit rate change request could have been made in another word of the synchronization group (the second one, like in the normal mode).
One can really wonder how this reduced mode prime frame is fabricated; indeed the digital multiplexer gates use the counter information which is used to identify the prime frames in normal mode; so how is the serialization of information performed in reduced mode???
Where it really becomes tasty is when they describe the way the transition from normal mode to reduced mode is made.
When the astronaut changes the bit rate selector from normal mode to reduced mode,the reduced bit-rate ID is inserted into the second word of the first prime frame of the subframe (to warn the receiver of the bit-rate change); the rest of the subframe is then processed in normal mode, for the change of bit-rate can only be done at the beginning of a subframe; the next subframe is then transmitted in reduced mode.
But, it is possible that the astronaut changes the selector after the second word of the first prime frame has passed, so it is too late to insert it into this word; in this case, the whole subframe is processed in normal mode, and, in the next subframe, the reduced bit-rate ID is inserted in the second word of the first prime frame of this new subframe, and this whole subframe is processed in normal mode again; it is only the next subframe which is (at last) processed in reduced mode.
This is perfectly stupid!; indeed, since the synchronization group exists in each prime frame of the subframe, the reduced bit-rate ID can be inserted in the second word of each prime frame of the subframe (to warn the receiver), so that the mode change can be done as soon as the end of the current subframe, and the next subframe can immediately be sent in reduced mode instead of sending it again in normal mode like in the process they described.
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Moreover this process only works if the receiver is listening at the moment of the bit-rate change.
If it starts listening after the bit-rate change, it will not be warned of the change.
There is a more efficient way to detect the bit-rate change, and which works at any moment, even if the receiver starts listening after the bit-rate change:
Since a pulse is 32 times shorter in the normal mode than in the slow mode, the first word of a prime frame could contain alternating ones and zeroes: If the receiver detects a pulse which is 19.5 microseconds wide, it then knows the data is transmitted in normal mode, for it cannot happen in reduced mode; and, if the receiver detects no pulse having this duration in a 20 milliseconds interval (transmission time of a prime frame in normal mode), the receiver then knows that the data is transmitted in reduced mode, for this cannot happen in normal mode.
Anyway, having two bit-rates for the transmission of the DATA makes no sense.
if the DATA can be transmitted at 51200 bits/second, it must always be transmitted at this speed.
The low mode transmits much less information, and the way the data is serialized is much different from the way the information is serialized in normal mode, and totally unclear (the multiplexing of digital gates uses the information of the normal mode).
The only justification for having a reduced mode is that the CM could only receive the DATA at the low-bit rate, as they say.
But, if the carrier which conveys the DATA information to the CM has a frequency (259.7 Mhz) which is almost ten times smaller than the frequency of the carrier which conveys the DATA information to the earth (2282.5 Mhz), it is still 5000 times faster than the DATA's normal mode, that is largely fast enough to convey the DATA information in this mode.
Furthermore, the signal between the LM and the CM is very clean, since there are no atmospheric pertubations to pollute it.
So, there is absolutely no physical impeachement to transmit the DATA in the normal mode (51200 bits per second) from the LM to the CM.
The conclusion is that the slow mode doesn't have the least justification to exist (and on what basis would the astronaut change the bit-rate's selector?)
I think that the slow mode has just been created to give the NASA's engineers the occasion to devise an absurd way to change from one mode to the other.
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This schema, extracted from the LM's handbook, shows a digital multiplexer of the LM's electronic circuitry.
So, how does this multiplexer works?
I show it on a stage of this multiplexer.
When the word gate command is activated, the current goes through the resistors that the command is connected to.
The other ends of the resistors are connected to the bits of the corresponding input word.
When a bit of the input word is set to 0, the current can go through the diode on the left, and there is no current on the diode on the right; the bit on the right is also 0.
Conversely, when a bit of the input word is set to 1,the current cannot go through the diode on the left, and thence it goes through the diode on the right instead; the bit on the right is also 1.
So, couldn't the bits of the input directly be connected on the right, since the bits on the right just copy the bits of the input word when the word command is activated?
No, because, when the word gate command is not activated, there is no current through the resistors, and the bits on the left cannot go on the right, because they are blocked by the diodes of the left.
When the word gate command is not activated, the bits of the input are not copied on the right.
Therefore, the way this multiplexer becomes obvious: When the output bits of the multiplexer must copy the bits of an input, the corresponding word gate command must be activated, and all the other word gate commands must be disactivated.
Now, the diodes on the left are absolutely mandatory: If they are absent, the bits of the input data word can go on the right, even if the word gate command is disactivated.
It becomes no more possible to select which data word is to be copied on the output of the multiplexer, and the multiplexer acts as a mixer instead of a multiplexer, which is not its role.
This animation illustrates the way the multiplexer works: When the first word gate command is activated, the output bits of the multiplexer copy the bits of the first data word, when the second word gate data is activated, the output bits of the multiplexer copy the bits of the second data word, and so on...
So the multiplexer they show is correct, and works as a normal multiplexer?
No, in fact, because you can see that, except for the first stage of the multiplexer, the other stages have no diodes on the left: As I explained, without these diodes, the multiplexer cannot work normally, and it is not possible to select the data word which is to be copied on the output of the multiplexer.
This multiplexer is abnormal and cannot work.
I have added the missing diodes on the schema, which are necessary for the multiplexer to work normally.
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After the informations have been converted to digital, they must be serialized to be inserted into a train of bits.
This serialization uses a shift register of eight stages.
The serialization works the following way:
Each time a flip-flop receives a pulse on the shift control input (marked 'T'), it loads on its output the bit which is on its input; and the bit which is on its input is the output of the previous flip-flop of the shift register.
So, each time there is a shift pulse, the loaded bits will successively appear on the output of the shift register and will be inserted into the train of pulses.
This animation shows the way the shift register works: The bits initially loaded in the shift register successively appear on the output of the shift register, the shift pulse allowing to proceed each time to the next bit.
Before being shifted, the bits of the data word must be loaded into the shift register, and, after each eight pulses, they must be reloaded into the shift register, to be shifted again.
The bits of the data word are connected to the inputs I circled in red on the shift register.
But, there is a problem: The fact that the bits of the data word are connected to the shift register is not enough to load them into the shift register; there also must be a command to load them into the shift register, and, on the schema which is shown, this command is missing!
I have added this command on this corrected schema: A load command is connected to a load control input which exists on any normal shift register, and which will be triggered each eight shift pulses to load the next data bits to be serialized into the shift register.
If the data bits are not loaded with a parallel load command, then it is zeroes which will be shifted, and not the bits of the data input, and the data train will be flat.
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They use what they call a "Decision network".
This decision network receives two inputs, coming from what they call the "primary path" and the "secondary path", has three stages, and produces three outputs.
The primary path input is connected to each of the Schmitt triggers of the stages through a resistor via connections I outlined in green; the secondary path input is connected to each of the Schmitt triggers of the stages through a couple resistor/capacitor via connections I outlined in blue.
Therefore the inputs of the three trigger schmitts inside the decision network receive identical signals, and their outputs are also the same.
So, there is clearly here a triredundancy, for the outputs of the decision network produce the same signals.
What could be the reason for this triredundancy?
In case that one of the three Schmitt triggers fails, and the two other ones remain operative, the decision network could continue to work (eventually, it could even continue to work if two of the Schmitt triggers were failing).
But it is not at all the justification they give for this "triredundancy" (as they themselves call it), here is how they justify it:
"The triredundant circuit allows the phase locked oscillator (circled in violet) to continue driving the timing generator if the primary input from Trigger Schmitt D (barred with a red cross) does not appear at the decision network input".
THIS IS TOTALLY ABSURD!
Why?
Because, either the input from the primary path is not necessary to drive the timing generator, and then each output of the decision network could drive it, or this input is necessary, and then none of the outputs of the decision network will be able to drive it.
The result would be exactly the same if the decision network only had a unique stage!
The triredundancy of the decision network only has a meaning if one of its elements (Schmitt triggers) fails, not if one of its inputs (which are identically connected to the three stages inside the decision network) fails!
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After the decision network, there are several stages successively dividing the timing signal.
As these stages are the same, I represent here one of them.
We can see that the counters are repeated thrice in order to create a triredundancy (again!).
Each of the AND gates that the counters are connected to are connected to an OR gate.
The goal of this triredundancy is that, if two of the counters fail, the third one which is still working can still produce the timer signal on the OR gate (circled in orange); and the OR gate will output the timer signal if it receives it on any of its inputs, even if the two other inputs are forced to zero.
For instance, let's suppose that the two counters I have barred with a red cross are defective.
The outputs of the AND gates that they are connected to (that I have circled in red) are then forced to zero.
However, there is still a counter which is operative, so that the AND gate it is connected to (that I have circled in green) should produce a counter output that the OR gate should also output?
No in fact, for the other input of the gate that the working counter is connected to comes from a defective counter (I have outlined the connection in red); and this defective counter also forces the output of this AND gate to zero.
So, finally the OR gate receives three signals forced to zero, and will also output a zero signal.
And the connection is so made that if any two of the three counters are defective, then the outputs of the three AND gates will be forced to zero, and so will be the output of the OR gate.
So the triredundancy is made in an absurd way and doesn't fulfill its role of producing a timer output if two of the three counters are defective.
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The BCD coding (Binary coded digital) is a system which converts each digit of a decimal number into its binary equivalent on 4 bits; not all the combinations of the bits are used, for a decimal digit goes from 0 to 9, and 4 bits can count up to 15.
This is an example of time converted into BCD corresponding to 11 days, 13 hours, 45 minutes, and 30 seconds.
They say that they send the mission elapsed time in BCD format; as the maximal value of the tens digit is 3 for the days (days count from 0 to 39), that the maximal value of the tens digit is 2 for the hours (hours count from 0 to 23), that the maximal value of the tens digit for the minutes is 5 (minutes count from 0 to 59), and the maximal value of the tens digit for the seconds is also 5 (seconds also count from 0 to 59), the number of bits needed in BCD format is: 2+4+2+4+3+4+3+4=26 (other bits are always zero), and this is exactly the number of bits of the mission elapsed time that they say they send into the serialized data; but, if they had sent the mission elapsed time as a total count of seconds directly in binary,only 19 bits would have been necessary, and it would have saved 7 bits in the serialized data (the receiver can perfectly convert the binary information into BCD for the display).
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This schema shows the diagram of the circuit of the Master Alarm PushButton/Lights.
The two pushbuttons I have circled in red allow to switch off the lights K1, K2, and K3 (circled in pink).
But, they both have to be simultaneously pressed to switch off these lights.
If only one pushbutton is pressed, the lights will not be switched off.
Why is it necessary to simultaneously press the two pushbuttons to switch off the lights, when one would have been enough?
When the light K7 (circled in orange) is switched on, they say that it prevents the lights K1, K2 and K3 (circled in pink) from being switched off; but one can wonder how it is possible, for the light K7 has no action on the reset of the flip-flops which command the lights K1 to K3.
I'll also have a discussion on the block of switches I circled in violet.
Putting the switches K2B and K3B on the up position has the same effect as putting the switches K1A and K2A or K3A on the down position.
Putting the switch K5B on the up position has the same effect as putting the switches K5B and K7A on the left position; and they only have an effect if the switches K5A and K6A are both on the left position.
We here clearly have a redundancy in the position of the switches!
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There is then a whole part of the way alarm lights are switched on, it is quite tedious to read, and I haven't tried to find an incoherence in each of these lights.
However, I managed to notice some things in it.
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They say that the glycol alarm light is switched on either is a low coolant level is detected or if the temperature exceeds an acceptable limit, but setting the GLYCOL switch to INST inhibits the alarm and causes the alarm to go off.
So what is the problem?
The problem is that, as long as the GLYCOL switch is on INST, the alarm light will be inhibited from going on, and so the astronauts will not be warned there is a problem with the glycol.
It should not be a switch which should reset the alarm, but a pushbutton.
Of course, you could say that the astronaut has just to remember that he must change the switch again after the light has been turned off, but it is possible that he forgets, so it is unsafe.
With a pushbutton, it is safe, for the contact of the pushbutton will automatically be released with the astronaut stops pressing it.
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First they say that the ECS caution light goes on if both GLYCOL pumps are malfunctioning, and the ECS caution light goes off when normal coolant pressure is restored.
Then they say that, if suit fan No 1 malfunctions, both the ECS caution light and the SUIT FAN caution light go on.
There is no problem with the ECS caution light going on for two different reasons, but there is one with what follows:
If the SUIT FAN selector is set to 2, suit fan No 2 is selected, and both ECS caution light and SUIT FAN light are turned off.
If we read them literally (they have not said that the ECS caution light will be turned off if it has no other reason to remain on), that means that the ECS caution light can be forced off even though there may be a problem with the two glycol pumps; in that case, the astronauts will not be warned there is a problem with coolant pressure!
However, it is not confirmed by the electronic diagram.
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The heater failure detection light goes on when an element has a problem of temperature (out of bounds).
This light is common to several elements, so the astronauts don't know which element had the problem of temperature.
In order to know it, they must turn the TEMP switch (I circled in red) till the alarm light goes off; at that moment, they know which element had the problem of temperature.
This is hilarious: With a seven segment, the astronauts could directly have read the number of the element which had the problem (0 for no element in error, or the number of the element from 1 to 7).
The connections I show here (I show them alternately, otherwise the diagram would be overloaded) allow to directly display on the 7 segment the number of the error which is currently activated.
It is true that, in case that several errors happen in the same time, the display becomes incoherent, but still shows there is a problem (when there is no problem, all segments are off).
However, if there are several temperature problems in the same time, the light will not go off till the selector has been put on the last position corresponding to a problem of temperature; so there are positions which will clear a flip-flop which corresponds to an error of temperature, but which will not turn off the light; that means that there may be problems of temperature that the astronaut will not be aware of when several problems occur in the same time.
You may be a little confused about this, but with a little demonstration, I think it will become clear.
Suppose several temperature problems have occurred in the same time (or almost).
The first, third and sixth temperature signals have gone up and set the corresponding flip-flops (circled in red).
If any of the flip-flops is set, the alarm light goes on, so with three flip-flops set, the alarm light also goes on.
The astronaut sees the alarm light, so he knows there is a problem of temperature.
To know which element caused the problem, he first puts the selector on position 1; this position corresponds to a problem of temperature, and the corresponding flip-flop is reset; however, the light does not go off, because there are two other flip-flops which are still set; thence the astronaut delusively thinks there was no problem with this temperature signal, whereas there was one.
The astronaut then puts the selector on the third position; this position also corresponds to a problem of temperature, and the corresponding flip-flop is reset; however the light still does not go off, because there is still another flip-flop which is set; thence the astronaut thinks again there was no problem of temperature with this element, when in fact there was one.
Finally the astronaut puts the selector on the sixth position; this position corresponds to the last problem of temperature; the last flip-flop which was set is now reset, and, since all flip-flops are reset, the temperature warning light now goes off.
The astronaut then thinks that this is the only element which created the temperature problem and will not know that two other elements also created a temperature problem.
So, just to save some lights, the safety of the ship is seriously threatened because the astronaut is not informed of all the problems.
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They say this:
TCA's may not respond to all individual command signals if they are of short duration (less than 80 milliseconds).
After 6 pulses without a response, the next command pulse (even if accompanied with a response) enables the counter and causes the RCS TCA warning light to go on".
So, it means that the warning light may go on even though there has been a response (in the last pulse); the warning light would be on whereas there is no motive for it to be on as the response finally came!
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They say that the ASC QTY caution light goes on when the quantity of fuel or oxidizer remaining in the ascent tanks is sufficient for only approximately 10 seconds of burning time!
They also say that "manually shutting down the ascent engine prevents possible explosion due to depletion of either propellant before the other"; Since it appears so dangerous, couldn't this be done automatically since this detection is already automatic?; that means that, if the astronaut forgets to do it, or doesn't do it fast enough when he sees the light on, he might explode! LOL!
They also say that, "if feasible, the astronaut will prepare to use the RCS for thrusting".
And what if it is not feasible (an important thrust is still needed for the ascent)?
Is the astronaut instructed to make a prayer to the Virgin Mary then?
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They say that the CES AC warning light goes on to indicate an excessive increase or decrease from the GN&CS 28 volt...power supplies, but that momentarily setting the GYROTEST switch to POS RT or POS LEFT resets this light!
But it is not the role of the GYROTEST switch to reset an alarm light!
Suppose the astronauts need to change the GYROTEST switch and they have not noticed this alarm light was on: this alarm light will be switched off, and the astronauts will never have noticed it went on!
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They say that the ISS warning light goes on to indicate a failure in the inertial subsystem section of the power supply, the pulses integrating pendulous accelerometer during main engine thrusting, the gimbal servo, or the coupling data unit.
They say that this warning light goes off when the failure is corrected (which is normal), but also if the GUID CONT is set to AGS!
That means that, when the LM is guided with the AGS, it is not possible to be informed about these errors!
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They say that the RNDZ RDR caution light goes on if there is no tracking indication or if velocity data are not good.
Till then, OK!
But then they say that, when the RENDEZVOUS RADAR selector is set to AUTO TRACK, a signal resets the flip-flop, and the RNDZ caution light remains off even though a data-no-good condition may exist!.
Where it becomes particularly tasty is that they then say that if both no tracking indication and velocity-data-good signals are sent to the CWEA, a flip-flop is set and, if thereafter there is a data-no-good condition which occurs, then the warning light will go on because of the set flip-flop (and will go off when the data-no-good signal disappears).
This is hilarious, because, if the data-no-good condition persists after the RENDEZVOUS RADAR selector has been switched to AUTO TRACK, and the data-good-condition never occurs, then the alarm light will never go on, even though the data is not good!
That's really a strange logic, a lunar logic, shall we say!
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This is the diagram of the DSEA which allows the recording of informations.
A mode switch, I have circled in red, allows to determine the way the recording is started and stopped.
- In the VOX position, A VOX circuit (I have circled in orange) senses if the voice is talking or not; when the voice is talking, this circuit enables the recording, and when the voice is mute, this circuit disables it.
- In the PTT position the recording is enabled only when the astronaut presses a push-to-talk button.
- And, in the ICS/PTT position, the recorder is always enabled, except when the switch I have circled in blue is set to OFF.
When the ICS switch (I have circled in pink) is on the position ICS T/R, the voice is enabled for the recording; and when it is on the position ICS RCY, the voice is not enabled for the recording, which means that it is not recorded, even if the recording is active.
So, when the MODE switch in on the VOX position, and the ICS switch on the position ICS RCY, we come to this weird situation in which the voice starts or stops the recording whereas it is not recorded!
Does it make sense?
Four different informations are mixed to be recorded:
a) the first information to be recorded is the voice coming from the block I circled in red, provided that it has been enabled to be recorded (by setting the ICS switch on the position ICS T/R).
b) The second information to be recorded is the serialized data coming from the block I circled in orange.
Before being mixed with the voice, the data produces two different encoding signals: A 1 bit data produces a signal of 4.175 khz, and a 0 bit data produces a signal of 4.625 khz.
If the data is serialized at the normal bit rate (51200 bits per second), then a signal of 51.2 khz (more than ten times the frequency of the signals which stand for the 1 and 0 bits of the serialized data) would have a cycle which just fits into one bit of the serialized data; and the encoding signal would need to have several cycles fitting into one bit of the serialized data; that means that in fact it is rather signals of one hundred times greater frequency than the frequencies which are mentioned which should be used to encode the bits of the serialized data.
Now, if the data is recorded in reduced mode (1600 bits per second), then the encoding signals have a frequency high enough to encode the data bits, because several cycles of them fit into the bits of the data, but it is still unpractical: the 1 and 0 bits of the data shoud not be encoded with two different frequencies, but rather with the same frequency and two different amplitudes; the carrier of the data could then be separated from voice by a high-pass filter, and then the carrier eliminated by a low-pass filter.
c) The third information which is mixed to the signal which is recorded comes from the block I circled in blue and is called "BIAS OSCILLATOR"; it "eliminates nonlinear response in playback of voice and data"; this is hilarious, for neither the voice nor the modulated data have to have a "linear" response.
d) The fourth information comes from a reference oscillator (circled in green) which provides a constant 5.2 kc signal "for subsequent use in the DSEA test station, servoamplifiers"; this signal is absolutely useless and has no reason to exist; it unnecessarily overloads the recorded signal.
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