4. VIDEO DISPLAY PROCESSOR



    The 9929 VDP contains all the circuitry necessary to generate the video display. It appears to the Z80 as two I/O ports called the Data Port and the Command Port. Although the VDP has its own 16 KB of VRAM (Video RAM), the contents of which define the screen image, this cannot be directly accessed by the Z80. Instead it must use the two I/O ports to modify the VRAM and to set the various VDP operating conditions.

    The original version of "The MSX Red Book" documented the VDP ports associated to I/O addresses 98H and 99H, which are prevalent on most machines, but it is completely deprecated by MSX standard that foresees VDP expansions, which must use different I/O mapping to avoid conflicts with internal VDP. The MSX-BIOS contains two addresses that must be read to determine where the VDP read and write ports are mapped. These addresses are 0006H (read ports) and 0007H (write ports). On MSX, VDP has only two ports mapped. On MSX2, MSX2+ and turbo R, VDP has six ports mapped.

    Usage example:


Data Port


    The Data Port, which value is stored in BIOS address 00006H, is used to read or write single bytes to the VRAM. The VDP possesses an internal address register pointing to a location in the VRAM. Reading the Data Port will input the byte from this VRAM location, while writing to the Data Port will store a byte there. After a read or write the address register is automatically incremented to point to the next VRAM location. Sequential bytes can be accessed simply by continuous reads or writes to the Data Port.


Command Port


    The Command Port is used for three purposes:

  1. To set up the Data Port address register.
  2. To write to one of the VDP Mode Registers.
  3. To read the VDP Status Registers.

Address Register


    The Data Port address register (VRAM pointer) must be set up in different ways depending on whether the subsequent access is to be a read or a write. The address register can be set to any value from 0000H to 3FFFH by first writing the LSB (Least Significant Byte) and then the MSB (Most Significant Byte) to the Command Port. Bits 6 and 7 of the MSB are used by the VDP to determine whether the address register is being set up for subsequent reads or writes as follows:

    It is important that no other accesses are made to the VDP in between writing the LSB and the MSB as this will upset its synchronization. The MSX ROM interrupt handler is continuously reading the VDP Status Register as a background task so interrupts should be disabled as necessary. It is also important to prepare VDP for reading or writing every time the program needs to change from one operation to the other, that is, a program cannot read a byte from VRAM and, without setting VDP for writing, write a byte to the next address, or write a byte to VRAM and, after that, read a byte them the next address without preparing VDP for reading.


VDP Mode Registers


    The VDP has forty-seven write-only registers, numbered 0 to 46, which control its general operation. A particular register is set by first writing a data byte then a register selection byte to the Command Port. The register selection byte contains the register number in the six lower bits: 10RRRRRR. As the Mode Registers are write-only, and cannot be read, the MSX ROM maintains an exact copy of the part of the registers in the Workspace Area of RAM (Chapter 6). Using the MSX ROM standard routines for VDP functions ensures that those registers images are correctly updated.


Mode Register 0


    The External VDP (EV) bit determines whether external VDP input is to be enabled or disabled: 0=Disabled, 1=Enabled.

    The M3, M4 and M5 bits are three of the five VDP mode Selection bits that define the VDP display mode.

    The Interruption Enable 1 (IE1) bit, when set to "1", enables the line interruption, of which line number is defined by Mode Register 19. When the display raster reaches the defined line, an interruption is sent to the CPU. The Status Register 0 Frame Flag should be read to check if the interruption was not an end-of-frame interruption.

    The Interruption Enable 2 (IE2) bit, when set to "1", enables light-pen interruption. When the display raster reaches the light-pen sensor position on screen, an interruption is sent to the system. The Status Register 0 Frame Flag should be read to check if the interruption was not an end-of-frame interruption.

    The Digitizer (DG) bit, when set to "1", enables the colour bus input mode, capturing data into the VRAM.


Mode Register 1


    The Magnification (Mag) bit determines whether sprites will be normal or doubled in size: 0=Normal, 1=Doubled.

    The Size bit determines whether each sprite pattern will be 8x8 bits or 16x16 bits: 0=8x8, 1=16x16.

    The M1 and M2 bits determine the VDP operating mode in conjunction with the M3, M4 and M5 bits from Mode Register 0.

    The Interrupt Enable bit enables or disables the interrupt output signal from the VDP: 0=Disable, 1=Enable.

    The Blank bit is used to enable or disable the entire video display: 0=Disable, 1=Enable. When the display is blanked it will be the same colour as the border.

    The 4/16K bit alters the VDP VRAM addressing characteristics to suit either 4 KB or 16 KB chips: 0=4 KB, 1=16 KB.


Mode Register 2


    Mode Register 2 defines the starting address of the Name Table in the VDP VRAM. The four available bits only specify positions 00BB BB00 0000 0000 of the full address so register contents of 0FH would result in a base address of 3C00H.


Mode Register 3


    Mode Register 3 defines the starting address of the Colour Table in the VDP VRAM. The eight available bits only specify positions 00BB BBBB BB00 0000 of the full address so register contents of FFH would result in a base address of 3FC0H. In Graphics Mode only bit 7 is effective thus offering a base of 0000H or 2000H. Bits 0 to 6 must be 1.


Mode Register 4


    Mode Register 4 defines the starting address of the Character Pattern Table in the VDP VRAM. The three available bits only specify positions 00BB B000 0000 0000 of the full address so register contents of 07H would result in a base address of 3800H. In Graphics Mode only bit 2 is effective thus offering a base of 0000H or 2000H. Bits 0 and 1 must be 1.


Mode Register 5


    Mode Register 5 defines the starting address of the Sprite Attribute Table in the VDP VRAM. The seven available bits only specify positions 00BB BBBB B000 0000 of the full address so register contents of 7FH would result in a base address of 3F80H.


Mode Register 6


    Mode Register 6 defines the starting address of the Sprite Pattern Table in the VDP VRAM. The three available bits only specify positions 00BB B000 0000 0000 of the full address so register contents of 07H would result in a base address of 3800H.


Mode Register 7


    The Border Colour bits determine the colour of the region surrounding the active video area in all four VDP modes. They also determine the colour of all 0 pixels on the screen in 40x24 Text Mode. Note that the border region actually extends across the entire screen but will only become visible in the active area if the overlying pixel is transparent.

    The Text Colour 1 bits determine the colour of all 1 pixels in 40x24 Text Mode. They have no effect in the other three modes where greater flexibility is provided through the use of the Colour Table. The VDP colour codes are:


VDP Status Registers


    Reading the Command Port will input the contents of the VDP Status Registers. On MSX, there is only one status register. On MSX2, MSX2+ and turbo R, there are ten status registers (from S0 till S9), which are selected by Mode Register 15.


VDP Status Register 0


    On MSX, this is the only status register available:

    The Fifth Sprite Number bits contain the number (0 to 31) of the sprite triggering the Fifth Sprite Flag.

    The Coincidence Flag (C) is normally "0" but is set to "1" if any sprites have one or more overlapping pixels. Reading the Status Register will reset this flag to a 0. Note that coincidence is only checked as each pixel is generated during a video frame, every 1/60 s (on a UK machine this is every 20 ms). If fast moving sprites pass over each other between checks then no coincidence will be flagged.

    The Fifth Sprite Flag (5S) is normally 0 but is set to 1 when there are more than four sprites on any pixel line. On MSX2, MSX2+ and turbo R, this flag indicates when there are more than eight sprites in line. Reading the Status Register will reset this flag to "0".

    The Frame Flag (F) is normally 0 but is set to 1 at the end of the last active line of the video frame. This will occur every 1/60 s (for UK machines with a 50 Hz frame rate this will occur every 20 ms). Reading the Status register will reset this flag to a 0. There is an associated output signal from the VDP which generates Z80 interrupts at the same rate, this drives the MSX ROM interrupt handler.


Screen Modes


    The VDP has thirteen operating modes, each one offering a slightly different set of capabilities. Generally speaking, as the resolution goes up the price to be paid in VRAM size and updating complexity also increases. In a dedicated application these associated hardware and software costs are important considerations. For an MSX machine they are irrelevant, it therefore seems a pity that a greater attempt was not made to standardize on one particular mode. The Graphics Mode is capable of adequately performing all the functions of the other modes with only minor reservations.

    An added difficulty in using the VDP arises because insufficient allowance was made in its design for the overscanning used by most televisions. The resulting loss of characters at the screen edges has forced all the video-related MSX software into being based on peculiar screen sizes. UK machines normally use only the central thirty-seven characters available in 40x24 Text Mode. Japanese machines, with NTSC (National Television Standards Committee) video outputs, use the central thirty-nine characters.

    The central element in the VDP, from the programmer's point of view, is the Name Table. This is a simple list of single- byte character codes held in VRAM. It is 960 bytes long in 40x24 Text Mode, 768 bytes long in 32x24 Text Mode, Graphics Mode and Multicolour Mode. Each position in the Name Table corresponds to a particular location on the screen.

    During a video frame the VDP will sequentially read every character code from the Name Table, starting at the base. As each character code is read the corresponding 8x8 pattern of pixels is looked up in the Character Pattern Table and displayed on the screen. The appearance of the screen can thus be modified by either changing the character codes in the Name Table or the pixel patterns in the Character Pattern Table.

    Note that the VDP has no hardware cursor facility, if one is required it must be software generated.


40x24 Text Mode


    The Name Table occupies 960 bytes of VRAM from 0000H to 03BFH:

    Pattern Table occupies 2 KB of VRAM from 0800H to 0FFFH. Each eight byte block contains the pixel pattern for a character code:

    The first block contains the pattern for character code 0, the second the pattern for character code 1 and so on to character code 255. Note that only the leftmost six pixels are actually displayed in this mode. The colours of the 0 and 1 pixels in this mode are defined by VDP Mode Register 7, initially they are blue and white (on Japanese and European machines) or black and white (on Brazilian machines).


32x24 Text Mode


    The Name Table occupies 768 bytes of VRAM from 1800H to 1AFFH. As in 40x24 Text Mode normal operation involves placing character codes in the required position in the table. The "VPOKE" statement may be used to attain familiarity with the screen layout:

    The Character Pattern Table occupies 2 KB of VRAM from 0000H to 07FFH. Its structure is the same as in 40x24 Text Mode, all eight pixels of an 8x8 pattern are now displayed.

    The border colour is defined by VDP Mode Register 7 and is initially blue. An additional table, the Colour Table, determines the colour of the 0 and 1 pixels. This occupies thirty-two bytes of VRAM from 2000H to 201FH. Each entry in the Colour Table defines the 0 and 1 pixel colours for a group of eight character codes, the lower four bits defining the 0 pixel colour, the upper four bits the 1 pixel colour. The first entry in the table defines the colours for character codes 0 to 7, the second for character codes 8 to 15 and so on for thirty-two entries. The MSX ROM initializes all entries to the same value, blue and white, and provides no facilities for changing individual ones.


Graphics Mode


    The Name Table occupies 768 bytes of VRAM from 1800H to 1AFFH, the same as in 32x24 Text Mode. The table is initialized with the character code sequence 0 to 255 repeated three times and is then left untouched, in this mode it is the Character Pattern Table which is modified during normal operation.

    The Character Pattern Table occupies 6 KB of VRAM from 0000H to 17FFH. While its structure is the same as in the text modes it does not contain a character set but is initialized to all 0 pixels. The first 2 KB of the Character Pattern Table is addressed by the character codes from the first third of the Name Table, the second 2 KB by the central third of the Name Table and the last 2 KB by the final third of the Name Table. Because of the sequential pattern in the Name Table the entire Character Pattern Table is read out linearly during a video frame. Setting a point on the screen involves working out where the corresponding bit is in the Character Pattern Table and turning it on. For a BASIC program to convert (X,Y) coordinates to an address see the MAPXYC standard routine in Chapter 4.

    The border colour is defined by VDP Mode Register 7 and is initially blue. The Colour Table occupies 6 KB of VRAM from 2000H to 37FFH. There is an exact byte-to-byte mapping from the Character Pattern Table to the Colour Table but, because it takes a whole byte to define the 0 pixel and 1 pixel colours, there is a lower resolution for colours than for pixels. The lower four bits of a Colour Table entry define the colour of all the 0 pixels on the corresponding eight pixel line. The upper four bits define the colour of the 1 pixels. The Colour Table is initialized so that the 0 pixel colour and the 1 pixel colour are blue for the entire table. Because both colours are the same it will be necessary to alter one colour when a bit is set in the Character Pattern Table.


Multicolour Mode


    The Name Table occupies 768 bytes of VRAM from 0800H to 0AFFH, the screen mapping is the same as in 32x24 Text Mode. The table is initialized with the following character code pattern:

    As with Graphics Mode this is just a character code "driver" pattern, it is the Character Pattern Table which is modified during normal operation.

    The Character Pattern table occupies 1536 bytes of VRAM from 0000H to 05FFH. As in the other modes each character code maps onto an eight byte block in the Character Pattern Table. Because of the lower resolution in this mode, only two bytes of the pattern block are actually needed to define an 8x8 pattern:

    As can be seen from Figure 29, each four bit section of the two byte block contains a colour code and thus defines the COLOUR of a quadrant of the 8x8 pixel pattern. So that the entire eight bytes of the pattern block can be utilized, a given character code will use a different two byte section depending upon the character code's screen location (i.e., its position in the Name Table):

    When the Name Table is filled with the special driver sequence of character codes shown above the Character Pattern Table will be read out linearly during a video frame:

    The border colour is defined by VDP Mode Register 7 and is initially blue. There is no separate Colour Table as the colours are defined directly by the contents of the Character Pattern Table, this is initially filled with blue.


Sprites


    The VDP can control thirty-two sprites in all modes except 40X24 Text Mode. Their treatment is identical in all modes and independent of any character-orientated activity.

    The Sprite Attribute Table occupies 128 bytes of VRAM from 1B00H to 1B7FH. The table contains thirty-two four byte blocks, one for each sprite. The first block controls sprite 0 (the "top" sprite), the second controls sprite 1 and so on to sprite 31. The format of each block is as below:

    Byte 0 specifies the vertical coordinate (Y) of the top-left pixel of the sprite. The coordinate system runs from -1 (FFH) for the top pixel line on the screen down to 190 (BEH) for the bottom line, that is, there is an one-line delay, so sprites are shown one line below their defined vertical position. Values less than -1 can be used to slide the sprite in from the top of the screen. The exact values needed will obviously depend upon the size of the sprite. Curiously there has been no attempt in MSX BASIC to reconcile this coordinate system with the normal graphics range of Y=0 to 191. As a consequence a sprite will always be one pixel lower on the screen than the equivalent graphic point. Note that the special vertical coordinate value of 208 (D0H) placed in a sprite attribute block will cause the VDP to ignore all subsequent blocks in the Sprite Attribute Table. Effectively this means that any lower sprites will disappear from the screen.

    Byte 1 specifies the horizontal coordinate (X) of the top- left pixel of the sprite. The coordinate system runs from 0 for the leftmost pixel to 255 (FFH) for the rightmost. As this coordinate system provides no mechanism for sliding a sprite in from the left a special bit in byte 3 is used for this purpose, see below.

    Byte 2 selects one of the two hundred and fifty-six 8x8 bit patterns available in the Sprite Pattern Table. If the Size bit is set in VDP Mode Register 1, resulting in 16x16 bit patterns occupying thirty-two bytes each, the two least significant bits of the pattern number are ignored. Thus pattern numbers 0, 1, 2 and 3 would all select pattern number 0.

    In Byte 3, the four Colour Code bits define the colour of the 1 pixels in the sprite patterns, 0 pixels are always transparent.

    In Byte 3, the Early Clock bit is normally 0 but will shift the sprite thirty-two pixels to the left when set to 1. This is so that sprites can slide in from the left of the screen, there being no spare coordinates in the horizontal direction.

    The Sprite Pattern Table occupies 2 KB of VRAM from 3800H to 3FFFH. It contains two hundred and fifty-six 8x8 pixel patterns, numbered from 0 to 255. If the Size bit in VDP Mode Register 1 is 0, resulting in 8x8 sprites, then each eight byte sprite pattern block is structured in the same way as the character pattern block shown in Figure 26. If the Size bit is 1, resulting in 16x16 sprites, then four eight byte blocks are needed to define the pattern as below:

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