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How to display the strength of a net and its drivers

Swapnajit Mittra

Vineyard Research Inc.




Sometimes it is useful to see the following information about a net all in one place.

  • The logic value of the net
  • Its strength value
  • How the net has got these values: the logic and strength values of its drivers.
(During the debugging of a logic, if you ever had to chase an X on a net, you know what I mean!)

Unfortunately, there is no standard system call to find out what are the drivers of a net and what are their strength values. Verilog-XL provides a non-standard system call $showvars, which finds out the drivers of a net. But there is no system call to find out the origin of propagating Xs.

We are now going to see how to write such a PLI application. Note that, the term "strength" makes sense only for a wire - a bus or a reg can not have any strength. Since, strength makes more sense for gate level design rather than RTL or behavioral design, our system call $strength will assume a gate level model for the input design.

The following Verilog program shows how to use such a call. 

module top;
wire q;

   myand u1 (q, 1'b1, 1'b1);
   myand u2 (q, 1'b0, 1'b1);

   initial
   $strength(q); 
endmodule

module myand (c, a, b);
output c;
input a,b;

	and m1 (c, a, b);

endmodule

The code listing for $strength is shown below. 
#include "vcsuser.h"      
#include "acc_user.h"      

int myCalltf();
int myChecktf();
                                                               
int myChecktf()
{
   if (tf_typep(1) != tf_readonly)
      tf_error("The parameter must be a scalar net");
}

int myCalltf()
{
   handle net = acc_handle_tfarg(1), driver = null;

   io_printf(" Signal: %s, Strength: %s\n",
      acc_fetch_fullname(net),
      acc_fetch_value(net, "%v", null));

   io_printf(" Driving Strengths:\n"); 
   while (driver = acc_next_driver(net, driver)) 
      io_printf(" %s\t\t %s\n", 
         acc_fetch_fullname(acc_handle_parent(driver)),
         acc_fetch_value(driver, "%v", null));
}

Notice that the net q in our example should be at x, as there is a contention between the outputs of the two AND gates.

Here is the output of the Verilog program: 

 
 Signal: top.q, Strength: StX 
 Driving Strengths:           
 top.u2.m1               St0  
 top.u1.m1               St1

Vineyard Research Inc.