Re: [PROTEL EDA USERS]: What the .png file format is...

[Brian Guralnick <brian@innerdimension.com>]

    A .png file stands for 'Portable Network Graphics'.  It is the most
efficient ZERO-LOSS compression engine in that I know of.  The screenshot in
...gif would be about 160Kb, in jpeg, it would be about 350Kb with ugly
residue.  Until recently it wasn't popular cause a 2048x1536 image would
take a few minutes to compress with a 100Mhz cpu.  Since processing power
has gone up substantially, compressing .png now takes about 20 seconds with
a 500Mhz cpu.  Decompressing is now in seconds VS 10 to 20 seconds in the
past.  That is why it is not used web pages because slower PC would take
forever to create the displays.

    The best .png engine for compressing in inside Paint Shop Pro 6, by
Jasc.  Note that JPEG is still more efficient for photographs, like 10:1,
but it smudges things.  The .png format can cut the photos down around 4:1
without a single bit or pixel lots or smudged.

Glad to explain,
    Brian Guralnick.

----- Original Message -----
From: "Brooks Bill" <bbrooks@zoneworx.com>
To: "Multiple recipients of list proteledausers"
<proteledausers@techservinc.com>
Sent: Friday, September 01, 2000 11:29 AM
Subject: RE: [PROTEL EDA USERS]: Copy & paste within PCB P99SE with NETS
please.


> What is a PNG file? It came up great on screen!  I have not seen that
> extension before...
> - Bill Brooks
>
>
> -----Original Message-----
> From: Brian Guralnick [mailto:brian@innerdimension.com]
> Sent: Friday, September 01, 2000 1:03 AM
> To: Multiple recipients of list proteledausers
> Subject: Re: [PROTEL EDA USERS]: Copy & paste within PCB P99SE with NETS
> please.
>
>
> Hi everyone,
>
>     I created sorta a 'via funnell' to pass a buss over a group of SGRAM
> chips.  Annoyingly, my pasted copy was missing the net names.  Is there a
> simple way to transfer the nets so that my 2 via funnells may be joined
> without all the ERC?
>
> Illustration, 80Kb desktop screenshot:
> ftp://ftp.point-lab.com/quartus/Public/ProtelUsers/ptelcopy.png
>
>
>     One other thing, is there an automated way to build such a funnel to
try
> to keep a bundled set of signals as tight as possible?  I know it woul be
> easy to just make straight lines for the bundle, but I like to keep open
> room to place power plane vias for the adjacent ICs...
>
> Happy CADing,,,
>     Brian.
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