Re: [PROTEL EDA USERS]: Via size

[Abd ul-Rahman Lomax <marjan@vom.com>]

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At 04:48 PM 9/11/00 -0400, Hans wrote:
>Hi group,
>
>  I was wondering if there are any specific guidelines in setting the via
>size. The bigger the via, the more current can go through ... but the
>gain in cross-sectional area only goes up slightly with increasing
>diameters. Any thoughts on this?

Sure.

It is not only the via hole size to be considered, but the connection to 
the via hole at the board surface as well. Somebody, please check my math!

Take a copper PCB, X total copper thickness including plating. Consider a 
track of width W connected to that via. The via has pad diameter D and hole 
size H, all dimensions in mils. D>=W. (There is no reason to have a pad 
diameter smaller than the track connected to it.) I am going to assume that 
hole plating is 1 mil thick, which is a typical minimum specification.

As a first approximation, the middle H mils of the track will be connected 
to copper which is 1/X as thick, being the proximal wall of the via hole. 
The effective width of this track (compared to a surface track) is thus 
H/X. Then the outer portion of the track around the hole adds a total 
additional width of D-H. For the via pad/hole/track combination to have an 
effective width of W, the diameter of the pad must be such that H/X+D-H, or 
D-H*(X-1)/X, is equal to W.

Solving for D, it is W+H*(X-1)/X. This is the ATTACHMENT constraint.

Further, all the current eventually must pass through the via itself.

To be equivalent to the track, the circumference of the via hole wall must 
be at least X*W; thus the hole diameter must be at least X*W/PI. This is 
the HOLE constraint.

Now consider that the pad diameter D should be at least H+2*A, where A is 
the minimum required annular ring. A relatively conservative value for A 
for a via would be 10 mils. This is the ANNULAR RING constraint.

 From the attachment and hole constraints, the minimum pad diameter D would 
be W+(X*W/PI)*(X-1)/X.

This simplifies to:

minimum pad diameter D = W*(1+(X-1)/PI).

Thus we can see that the minimum pad size (from these two constraints) 
increases by a factor which is dependent only on the plating thickness.

Consider a 50 mil track, with 2 oz total copper, which is 2.8 mils. X thus 
equals 2.8, and the minimum pad to use to match the trace width would be 
1.57 times as large, or 79 mils.

The minimum hole size should be, from the hole constraint, 45 mils. The 
annular ring constraint is satisfied; the hole could be as large as 59 mils 
if the minimum annular ring is 10 mils.

To be equivalent to a 50 mil track, I'd use a via pad diameter of 80 mils 
and a hole size of something between 45 mils and 59 mils, probably 52 mils 
if there were no other considerations.

The minimum pad size gets even larger if the board has total 3 oz. 
copper.... The ratio would increase from 1.57 to 2.34.

For a given copper weight, the ratios would hold. Determine the narrowest 
track for a given current and temperature rise, then the minimum via pad 
size will be the track width times 1.57.

This is not what I have done in the past; these calculations surprised me a 
little. I did not expect the calculated pad diameter to be independent of 
the hole size! Adding additional holes in sequence does not improve the 
situation, a hot spot would still form around the first hole, as those 
electrons bump into each other in the crowded space and get angry. (That's 
what causes traces to heat up, isn't it? :-)




marjan@vom.com
Abdulrahman Lomax
P.O. Box 690
El Verano, CA 95433



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