Re: [PROTEL EDA USERS]: Autorouting questions

["Pat Rundle" <pat@opsys.co.uk>]

Autorouting nets with differing widths over their length seems to be a
problem, also present in 99SE. The only (partial) way round this seems to be
to autoroute after setting the design rule for the minimum width (5mil) and
then change the rule to 13mil and autoroute again. I think you would have to
keep the clearance rule to 5mil everywhere. This sometimes works reasonably
well - I have routed power supply tracks to PGA before using this method by
increasing the rule from 5mil to 10mil then 20mil then 40mil and autorouting
between each change.

Pat

----- Original Message -----
From: "Tom Reineking" <reineking@pasco.com>
To: "Multiple recipients of list proteledausers"
<proteledausers@techservinc.com>
Sent: Monday, September 25, 2000 5:18 PM
Subject: [PROTEL EDA USERS]: Autorouting questions


> Hi all -
>
> I have a design that uses a 456-pin BGA thru-hole socket, S1, placed at
> the center of a pentagon shaped 6-layer board with 96-pin headers
> surrounding the socket.  The BGA pads are 35mil with 25mil holes at
> 50mil spacing. It works with 5mil tracks/5mil clearance (actually there
> is a problem here but stated later).  The problem is that the
> requester's spec needs 13mil tracks after leaving the BGA.  I have an
> old DOS approach that works but the thought of using it makes me ...
> Anyhow, I tried several approaches, none of which worked.
>
> 1.  Design rules:  clearance: scope (net class = all nets and component
> S1), different nets only, 5mil gap.
>   clearance: scope (board-board), different nets only, 7mil gap.
>   width: scope (region, area surrounding S1), 5mil max, 5mil min.
>   width: scope (board), 13mil max, 13mil min.
>
> I thought that this would force the autorouter to use 5mil tracks within
> S1 and 13mil tracks elsewhere.  It just used 13mil tracks and of course
> it would not route to interior pins of S1.
>
> 2.  I manually routed 5mil tracks from interior S1 pins to vias located
> outside of S1.  The vias did pick up the net names correctly.  The
> autorouter considered all of the 5mil tracks DRC errors, circling each
> BGA pin with a DRC marker.  The design rules had not been changed from
> above.  The autorouter will not route one net from a via even though the
> rats nest starts at the via indicating that the data base accepted the
> 5mil tracks as legitimate.
>
> Is there any good documentation out there that describes in more detail
> than Protel's stuff about the subtleties of selecting design rules?
> Another mystery is that with 35mil pads and 50mil spacing there is a gap
> of 15mils but I can't route a 5mil track with 5mil spacing on either
> side.  If I reduce the pads to 34mil then all is fine.  Is there another
> tolerance that I'm not setting in some obscure location?  One last
> request.  In another test I placed some free vias in an array and of
> course their net property was "no net".  I could not manually route to
> those vias because of the no net attribute.  If I change the attribute
> to the correct net name, then I could manually route to it.  Wouldn't it
> seem reasonable to have the via automatically change to the proper net
> name?  If this isn't reasonable, is there another way to do this?
>
> Thank you in advance for any light that anyone can shed.
>
> Cheers,
> Tom
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