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NP Computer Hardware page IRQ, I/O address Table, DMA controller |
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Interupt Request (IRQ) When a hardware device needs the CPU to do something,
such as when the keyboard needs a keystroke to be processed, the device
passes a number, called an interrupt
request number or IRQ, to the
CPU. This signals to the CPU that the device has a request that needs
processing. (This process of a hardware device needing attention from the CPU
is often referred to as "needing servicing.") During the boot process,
a unique IRQ is assigned to each hardware device that requires one, and
uniquely identifies that device, as well as the software that controls it. A device requires an IRQ if it can initiate an action or
provide input to the computer. Of course, the IRQ is simply a number, and the
CPU needs instructions on what to do, which it finds using the I/O address table (also called the interrupt vector table or the vector table), where I/O stands for
input/output. The I/O address table correlates each IRQ with the memory
address that holds the start of the program the CPU needs to process the
request from the device. Remember that during the boot process, each System
BIOS program and device driver is assigned memory and the memory address of
the start of each program is stored in the I/O address table at that time.
So, the CPU searches the vector table for the IRQ it receives, looks up the
memory address where the program it needs starts, and goes to that address to
execute the right software to process the request. Some devices that are assigned IRQs include the disk
drive, the mouse, and the keyboard. The CPU uses an IRQ to identify the
peripheral and find the software that controls it. In figure (NP fig 1) we see the hardware and
software layers involved in managing a mouse. When we move the mouse or click
one of its buttons, the mouse sends the IRQ to the CPU and writes the data to
a special area of the I/O address table to be read later by the request
handler. (A request handler is the System BIOS program or device driver that
handles the I/O request.) When the CPU receives the IRQ, it runs to the I/O
table for the location of the device driver, and in run to the device driver
to obtain instructions on how to interpret the data received. The mouse
driver reads the data and interprets and sends the data on to the OS which in
turn sends the data to the applications software currently running.
Software layers for operating a mouse The I/O Address Table The memory addresses assigned to device drivers and
System BIOS programs are stored in the I/O address table. This table is
located at the very bottom of the memory addresses (low numbers), sometimes
referred to as I/O addresses. For example, when the IRQ for the mouse signals the CPU
for service, the CPU looks in the I/O address table for the address in either
conventional memory or upper memory where the device driver or System BIOS
program that services the mouse is located. Device drivers must first be
copied to RAM because they are stored on the hard drive and cannot be
executed from there. Device driver files are copied to RAM and assigned
memory addresses during the booting process. The driver files may be loaded
into conventional memory or upper memory. (That conventional memory is the
first 640K of memory addresses; upper memory is the next 384K of addresses.) Both System BIOS and device drivers require two
different entries in memory as follows (see NP fig A) ·
An entry in the I/O address table, which correlates
device drivers and System BIOS programs with their starting addresses in
memory. ·
A block of memory addresses that contains the driver or
BIOS program In
summary, as shown in the NP fig A, the I/O address table – a block
of memory locations near the bottom of memory (low memory addresses) – is the
region of memory where the beginning addresses of the device drivers and BIOS
programs are stored. Think of the I/O address table as a mailbox containing
the number of another mailbox. Each IRQ is associated with a certain memory
location in the I/O address table. When the IRQ is received, the CPU uses
this value to determine which memory location in the I/O address table holds
the location of the device driver of BIOS. It then turns to this beginning
address location to retrieve the program to process the request.
DMA
Controller
The DMA
(direct memory access) controller on a motherboard (systemboard) is part of
the chip set and provides faster memory access because it handles the
movement of data in and out of RAM without involving the CPU. The DMA chip is
also responsible for dynamic memory refreshing that we discussed earlier. A
DMA chip traditionally offers four channels: 0, 1, 2, and 3. Channels 0 is
used for dynamic memory refresh; channel 2 is used for a floppy disk drive
controller, and channel 3 is used for a hard disk controller. That leaves
channel 1 available for some other device to write directly to RAM, bypassing
the CPU. Some computers have two DMA logical chips, making a total of 8
channels for input to RAM. Conflicts
with DMA channels can occur. When adding a second hard drive, CD-ROM drive,
or floppy disk drive, check which DMA channel the device uses if you suspect
a conflict. The documentation for the device should give you the information
you need. During the installation, you probably can change the DMA default
channel using a DIP switch or jumper if there is a conflict. This example
demonstrates how important it is to safeguard your documentation. Again, if
the new device is Plug-and-Play, Windows 95 does the work for you. |
