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                                  Parmanand V Mishra ( Analog Design Automation)
 

Abstract:

 This paper proposes a CMOS ,  PTAT ( proportional to absolute temperature) band gap reference (BGR)  circuit , which can be used for low
voltage power supply. In conventional BGR circuit designer were using BJT technology in which built in diode voltage and thermal voltage
were compensating each other. This paper describe design of PTAT-BGR circuit based on CMOS opamp[2], diode and poly resistor in 0.18u
MOSIS technology. Mesured Voltage Reference is 0.69 v.
 

INTRODUCTION :

An ideal bias generator should be insensistive with supply voltage, temperature and technology. In most IC design where BJT or parasitic BJT
are used  BGRs are designed using the diode built in  voltage ( VBE )  and thermal voltage ( U=kt/q) . It's easy to design in BJT and these BGRs
have excellent performance[4][5].
 
 
 

Vref= V1+(R2/R3) V2
V1= Built in Voltage of Diode
V2= KT/Q ln ( R2/R1)

V1 has negative temperature coefficient and V2 has positive[3] . So temperature effect is cancelled and Vref is controlled by R2 and R3 [4]
[1]. Using enhancement and depletion mode technology  voltage reference can be design using difference in thresholt voltage of
enhancement mode and depletion mode transistors[5]. But one more step is needed to have enhancement and depletion mode transistors on
same chip. In these days CMOS is most popular in IC design even  for analog circuits. It's very defficult to design BGR using CMOS for low
voltage and low power.
 

PROPOSED CIRCUIT:
 
 
 

There are different type of PTAT circuit proposed by designers [7]. In this circuit nmos and poly resistor are used to cancell the temperature effects.
In this circuit M0~M3  differencial amplifier ,M4~M8 and Rpoly is used to have desired output and M9~M10  and IDC is used to bias the differencial
cell.

VREF= Vtn + Ibias* Rpoly

where Vtn is threshold voltage of nmos ,Ibias is bias current through poly resistor, Rpoly is poly resistance. Vtn has negative temperature coefficeint
and  Rpoly  has positive tempereture coefficient so first order temperature effects are cancelled at the output.
There is two stable points for this circuit, in one case current through Rpoly could be negligible.

To avoid undesired point a startup circuit should be used with this circuit[8]

EXPERIMENTAL RESULT:

circuit is designed using 0.18u MOSIS technology and 1.8 v power supply. The reference  voltage is 0.69 V. Peak to peak variation in reference voltage
 is 162 mv in sweeping temperature from -40C to 120C.
 
 

technology	0.18U
Reference Voltage	0.69V
Peak to peak Vref Variation ( in sweeping temp from -40C to 120C)	162mv
Supply Voltage	1.8V
Noise density@10KHZ	100.7nv/sqrt(hz)
Max power dissipation	248.6UW

       Measured VREF characteristic as a function of temperature
 
 
 
 

 Measured DC characteristic of PTAT  circuit.
 

OPTIMIZATION:

this circuit  is optimization using  Genius (  An optimization tool from Analog  Design Automation )  for different specifications and different
combination of specifications.

Results after Optimization

After optimizing designer have flexibility to choose any desired circuit. Result can be brows using  Explorer-Genius
( A Tool to brows results after optimization from  Genius).

Results after Deleting Undesired output

Designer can select any plot and get the circuit curresponding to selected plot.
 

CONCLUSION:

this paper shows a PTAT BGR  design and optimization in CMOS  0.18u MOSIS technology. Using optimized result designer have great flexibility to
choose circuit  with different specification without going in detail  of design.
 

REFERENCES:
 

[1] Band Gap reference Voltage source
          hasan babare , Donald E zimmernan
[2] Analog  Integrated Circuit Design
         Ken And Martin
[3] A CMOS band gap reference circuit with 1 v operation
          Hironori banka hitishishiqa
[4] A precision curvature compensated Cmos Band gap reference
     Bang-sup Song and Paul R gray
[5] Low Power Cmos On chip voltage reference using mos PTAT - an EP approch
         Yoon derek seo
[6] A cmos band gap without resistors
       Arne E buck
[7] Temperature compensation Circuit technique fir high density CMOS DRAM
        Dong Sung ming, Sooin cho
[8] Band Gap Reference For Near 1-V operation in standard CMOS technology
         Andrea Pierazzi Andrea Boni Carlo Morandi