µP's interface to the external world through their pins or terminals which carry:

• Power
• Clock pulses
• Signals by which the µP intercommunicates with Memory, I/O, and possibly other µPs.

1. Power and Clock

   Typically, 8-bit µPs have one ground pin and one voltage pin (reference to the ground). Some 16-bit and 32-bit µPs have two or more ground pins and an equal number of voltage pins.

   Like the CPUs of most computers, µPs are synchronous machines which depend on clock pulses to synchronize their operations. Both the activation and deactivation of control signals (inside and at the external interface) relate to the edges of the clock. Usually, the clock pulses are supplied from an external source through the Clock Line.

2. Address Bus

   This set of signal lines identifies the location that is to be accessed by the CPU during a read or write operation. Such a location can be a Memory Location or and I/O Location, which stores one byte of data. The set of different addresses we can specify over the address bus constitutes the Direct Address Space of a µP.

   If we assume N address lines, then the Address Space is equal to 2ⁿ byte locations, wherein:

   0 (zero) - lowest address

   2^n-1 - highest address

   

   External CPU interface

   
   

   In 16-bit µCs, byte locations are usually paired into 16-bit word locations wherein:

   Even Address Byte - constitutes the upper half of the word

   Odd Address Byte - immediately constitutes the lower half

   Words are usually addressed by using the address of the upper byte and a control signal indicating that it is a word, not a byte address.

   In 32-bit µCs, byte locations may be grouped four at a time to form 32-bit word locations.

   Example:

   A particular 16-bit µP has 23 address lines. Determine its memory address space in Megabytes (MB). Up to how many 16-bit words can we possibly store in its memory?

   • Memory address space in MB

     2ⁿ = 2²³ = 8388608 bytes = 8 MB

   • Up to how many 16-bit words can we possibly store in its memory?

     8388608 bytes X 16 bits / 2 bytes X 1 word / 16 bits = 524288 words

   Some CPUs have a single Address Space for both memory and I/O locations. Others have two separate address spaces: a Memory Address Space and an I/O address Space. In such cases, the Memory Address Space is again 2ⁿ byte locations, while the I/O Address Space is much smaller, so only the Low-order Address Lines are used to transmit I/O Addresses.

   

   Division of Memory into Bytes and Words

   Example:

   The Address Bus of a 16-bit µP consists of 23 lines. However, when addressing I/O locations, it employs only the 16 Low-order Address Lines. Calculate the I/O Address Space of this CPU. What is the highest I/O Address?

3. Data Bus

   These lines carry the data to be written or read from the location identified through the Address Lines. Unlike Address Lines, which are undirectional, Data Lines may transmit information in either direction. The number of Data Lines determines the maximum amount of information we can transfer during a single read or write operation. In fact, it constitutes the bases for the categorization of CPUs.

   Example:

   If the Data Bus is 8-bit wide, then the CPU is considered to be an 8-bit µP.

4. Data Transfer Control Lines

   All information is communicated by means of the Data Transfer Control Lines. In the case of our Hypothetical µP; it uses six signals for this purpose. Three of these signals are meaningful whether in their true state or false state. The other three are only meaningful in their true state.

   • Memory - I/O (M/IO*) - this signal is only required if a CPU bus has a different I/O Address Space

   • Read/Write (R/W*) - this line indicates the flow of data transfer
     • If HIGH, the µP reads data from the Address Locations
     • If LOW, it writes data in the Address Location

   • Word/Byte (WRD/B*) - this signal indicates whether a byte or a word is to be accessed
     • If HIGH, Word Access Mode, the CPU simultenously accesses two bytes: one from the Even Address Byte and one from the immediately following byte
     • If LOW, Byte Access Mode, only a single data byte is specified over the Address Lines to be transferred.

   • Address Strobe (AS) - the CPU activates the AS to indicate what it has placed over the Address Lines to be transferred.

   • Data Strobe (DS) - this line plays a dual role
     • Write Operation, indicates that the CPU has placed information over the Data Bus
     • Read Operation, indicates to memory (or I/O) when to place information on the Data Bus

   • Ready - this signal is generated by external circuits to indicate that the memory and I/O readiness is in the process of Data transfer

   Steps of a Read Sequence (Assuming that the CPU is about to read one byte of data from memory)

   1. The CPU raises to HIGH the M/IO* and R/W* line to indicate this is a memory read operation. At the same time, it brings WRD/B* to a LOW to indicate a byte transfer and emits the address of the desired memory location into the Address Bus
   2. CPU activates AS indicating that the Address Bus carries a valid address
   3. The CPU raises to HIGH DS, the CPU samples the state of the READY line
   4. Data is located by the memory on the Data Bus
   5. CPU reads data and deactivates DS
   6. Following the deactivation of DS, the CPU deactivates AS and the remaining data transfer control lines, and the memory removes itself from the Data Bus.
   
   
5. Interrupt Lines
   • Interrupt Request (INTREQ) - Peripheral devices activate this line to report the availability of a new block of data or the existence of a failure condition. This line is a Maskable Line, that is, a program may choose to inhibit interruptions of the CPU by turning off the interrupt-enable bit of the Status Register. The masking mechanism allows us to prevent the disruption of the CPU by events whose priority is lower than one of the task currently being processed.

   • Interrupt Acknowledge (INTACK) - The CPU activates this line to indicate the fact state above

   • Non-Maskable Interrupt (NMINT) - Interrupts through this line are honored unconditionally, that is, they cannot be masked through the Status Register. The mechanism of program interruption remains the same except that the starting address of the service routine is determined internally by the CPU.
   
   
6. Bus Control Lines

   Some I/O devices are capable of transferring data to/from memory on their own (as we will see later). To do so however, they must gain temporary control of the Address Bus, the Data Bus, and some of the Data Transfer Control Lines. Thus we need some means of transferring bus control from the CPU to the I/O devices and back to the CPU. Our CPU has three lines for this purpose, namely:

   • Bus Request (BR)

   • Bus Grant (BG) - serves to acknowledge a bus request

   • Lock - indicates to I/O devices whether the CPU allows bus requests at this time