| Date of Birth | 12 June 1973 |
| Sex | Male |
| Nationality | Indian |
| Languages Known | English, Hindi, Punjabi |
| Father's Name | Mr. Sarban S. Parmar |
| Permanent Address | HNo-356, Udham Singh Nagar, Phagwara, Punjab, India. PIN:144401 |
Objective:
A technically challenging job in the field of EDA Tool Design with focus on System-Level, High-Level or RTL-Level Synthesis.
Experience:
1.
Software Engineer
Duration:
Oct-99
to Till-date
Company:
IKOS
India Pvt. Ltd., Noida.
Projects:
1.Worked
on this project till March-2000:
"Compilation of VHDL/Verilog RTL Code to generate
Gate-Level netlist."
2.Currently Involved with this project:
"Compilation of VHDL/Verilog Behavioral Description
and generate RTL code."
Software:
C,
C++, VHDL, and Perl/Shell-Scripting (All on Sun-OS)
2. Associate
Software Engineer
Duration:
Mar-99 to Oct-99.
Company:
SGS-Thomson
Microelectronics Ltd., Noida
Project:
"Study,
Design and Implementation of Technology Mapping
tools for FPGA based design, that maps the design to a
generic FPGA Architecture."
Software:
C,
C++ on Unix
3.
Research Associate
Duration:
July97
to Feb-99
Company:
Indian
Institute of Technology, Delhi.
Project:
"Synthesis
of synchronous digital system
from VHDL behavioral description."
Software:
C
on Unix platform
4. Software
Developer
Duration:
May96
to July97.
Company:
Engineers
India Ltd. Gurgaon, N. Delhi.
Project:
"Design
and Implementation of a GUI for Advanced Control
Models handling Simulation, Optimization and Control of
petroleum distillation control process."
Software:
Visual
C++ on MS-Windows/Pentium
Computer Literacy:
o Platforms:
Solaris, SunOS, HP-UX, WinNT, Linux
o Languages:
C, C++, Perl, Basic
o HDLs:
VHDL, Verilog and NDL
o Compiler Tools:
Lex, Yacc
o Others:
Unix Network Programming, C-Shell Scripting, Makefiles
Education:
|
Examination |
|
|
|
|
|
|
Delhi |
& Engineering |
|
|
|
|
Kanpur |
Engineering Minor:Computer Science & Engineering |
|
|
|
|
Punjab(PSEB) |
Punjabi, English |
|
|
|
|
Hoshiarpur, Punjab(PSEB) |
Social Science, Punjabi, English |
|
|
Other Examinations:
Major Projects:
* M.Tech Project: Data
Path Synthesis
Done
under Prof. M. Balakrishnan. The
high level
synthesis from behavioral description in VHDL is carried
out in
two stages viz., data path and control synthesis.
This project
involved the data path synthesis. The key steps
involved are
scheduling, allocation and binding. The system developed
takes
care of
+ Optimal Clock Period Selection
+ Operator pipelining, multicycling and chaining
+ Multifunctional Operators
* VHDL-to-IR (Intermediate
Representation) Compiler
Done
under Prof. M. Balakrishnan. The textual
behavioral
description of a digital system in VHDL is not a convenient format
for the tools that synthesize a circuit using an ASIC library
to
realize that behavior. This software
translates the VHDL
description to IR, which is a data
structure, organized as
records. The syntax of VHDL description
is checked before
generating IR. This work was implemented in C, LEX and YACC.
* VHDL-to-CDFG and CDFG-to-VHDL
Translators
Done
under Prof. M. Balakrishnan. This tool
reads VHDL
behavioral description and generates a disjoint Control Data Flow
Graph for scheduling/allocation. The tool CDFG-to-VHDL writes the
VHDL description from the scheduled/allocated CDFG.
* VHDL Beautifier
Done
under Prof. M. Balakrishnan. This program beautifies the
VHDL description by taking care of
indentation and keyword
alignment.
* BLIF-to-VHDL Translator
Done
under Prof. Anshul Kumar. This program takes as input
the BLIF description of a netlist mapped to a specific
library.
The output of the program is Structural Description of the circuit
in VHDL which is the implementation of the circuit using the
component library used for technology mapping.
* Implementing INTERCONNECT
ROUTING
Done
Under Dr Sharad Malik. The project involved implementing
interconnect topology design and a delay model for a network that
has gone through logic synthesis, technology mapping and placement
of cells. The earlier stages are implemented in a public
domain
tool from berkeley called SIS. Our
routing package is then
integrated with SIS package. Language: C/Unix
* Description of the
8251(USART) chip in VHDL
Done
under Prof. Anshul Kumar. Only the receiver part of the
chip was simulated for the 8251, which
is the Universal
Synchronous Asynchronous Receiver Transmitter. The coding was done
in VHDL.
* Hardware Prototype
for IBM Data Encryption Standard (DES) on FPGA
Done
as a part of FPGA course under M. Balakrishnan. DES is a
public key data encryption algorithm. Its software implementation
is very slow with a limited data encryption rate.
In hardware,
pipelining and parallelism can be used to break the performance
barriers. We designed a circuit, pipelined it at two levels. Then
the architecture was modified to
use two copies of the
computational part so as to fully utilize the FPGA chip and double
the data rate.
* Implementation of
a WhiteBoard Environment
Done
under Prof. Subrat Kar. This program was a prototype of
the Web Server Chat on the Internet with the additional utilities
for drawing graphics i.e. many users can edit a common graphics
sheet. The program was implemented as a client server model using
TCP sockets. The coding was done in Visual C++
Extra Curricular:
Date:
April,
2000
Place:
Noida
