Figure 8.15. In part eh there are 3 inputs, eh, b and c. Each one goes to the input of its own inverter. The outputs of the three inverters go to the input of an OR gate. The output of the OR gate goes to D. In part b there are 3 inputs eh b and c. They all feed into a NAND gate. The output of the NAND gate is D. End verbal description.
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