Figure 8.19. This circuit consist of 2 3-input NAND gates and 6 2-input NAND gates. They will be described in pairs moving from left to right. Gates 1 and 2 are the 3-input gates. The J input goes to one of the inputs of Gate 1. The K input goes to one of the inputs of gate 2. The second set of inputs of gates 1 and 2 are tied together and connect to the CK, clock, input. We will pick up the third set of inputs at the end. The output of gate 1 goes to one of the inputs of gate 3. The output of gate 2 goes to one of the inputs of gate 4. The output of gate 3 goes to the other input of gate 4. The output of gate 4 goes to the other input of gate 3. The output of gate 3 goes to one of the inputs of gate 5. The output of gate 4 goes to one of the inputs of gate 6. The Ck input goes through a level shifter to the input of an inverter, not numbered. The output of the inverter goes to the remaining inputs of gates 5 and 6. The output of gate 5 goes to one of the inputs of gate 7. The output of gate 6 goes to one of the inputs of gate 8. The output of gate 7 goes to the remaining input of gate 8. The output of gate 8 goes to the remaining input of gate 7. The output of gate 7 goes back to the remaining input of gate 2. The output of gate 8 goes back to the remaining input of gate 1. The output of gate 7 goes to the Q output. The output of gate 8 goes to the not Q output. End verbal description.
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