Figure 8.20. In part eh there is the block symbol for a JK flip-flop. The symbol is a rectangle that is twice as high as it is wide. On the right are the J, Ck, and K inputs. There are two more inputs at the top and bottom, they are direct set S and clear CL respectively. The Q and not Q outputs are on the right. On the left of the circuit are two inputs labeled data and clock. The data terminal goes to the J input. The data terminal also goes to the input of an inverter. The output of the inverter goes to the K input. The clock terminal goes to the Ck input of the flip-flop. The set and clear inputs are not connected. Part b shows a type D flip-flop. The S, CL, Q and not Q are placed the same as in the JK flip-flop but on the left instead of the three inputs are two labeled D and CK. The data terminal goes to the D input and the clock terminal goes to the Ck input. End verbal description.
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