Figure 8.31. This is the internal configuration of the 555 timer IC, not the internal schematic diagram. Remember, we are inside the IC looking out. Pin 8, V plus, connects to a chain of 3 resistors in series going to ground. Pin 1 of the IC is ground. All three are labeled as R and have a value of 5 k ohms. The junction of the top and middle resistor goes to the inverting input of a comparator. The noninverting input goes to pin 6, threshold. The output goes to the R input of a simple set and clear flip-flop. The junction of the top and middle resistors also goes to pin 5, control input. The junction of the middle and bottom resistors goes to the noninverting input of another comparator. The inverting input goes to pin 2, Trigger input. The output of this comparator goes to the S input of the flip-flop. Pin 4, reset, goes to the base of a PNP transistor. The emitter goes to a point labeled V ref. The collector goes to the reset input of the flip-flop. The not Q output of the flip-flop goes through a resistor to the base of an NPN transistor. The emitter is grounded. The collector goes to pin 7, discharge. The not Q output also goes to the input of an inverter. The output of the inverter goes to pin 3, output. End verbal description.
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