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Mixed Signal Devices For RF Signal Processing

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Document Summary of Contents

	This article describes Mixed Signal Devices suitable for RF applications. MATHCAD demonstrations are included and basic signal processing operations, such as Windowing time domain data and FFT analysis are included. Some worked design examples are included.
		CONFIDENTIAL This document is not to be copied, discussed, transferred electronically or otherwise, or shown to any party without prior written consent from the Author.   DISTRIBUTION. By Author’s Consent.

 

1        Table of Contents

1    Table of Contents........................................................................ 2

2    Preface....................................................................................... 4

2.1    Purpose of This Document.................................................................................................................................. 4

2.2   Topics Covered.......................................................................................................................................................... 4

2.3   Exclusions.................................................................................................................................................................. 4

3    Introduction To Digital / Analogue MSD’s........................................ 5

3.1    Motivation For Mixed Signal Devices (MSD).......................................................................................... 5

3.2   Definitions................................................................................................................................................................ 5

3.2.1     Quantization....................................................................................................................................................... 5

3.2.2     Bit Resolution..................................................................................................................................................... 5

3.2.2.1   MATHCAD Demonstration of Signal Quantization................................................................................ 7

3.2.2.2   MATHCAD Demonstration Of Effect Of Quantization On SNR....................................................... 8

3.2.2.3   MATHCAD Estimation Of Quantized Signal SNR in dB....................................................................... 8

3.2.3     Discrete Time Sampling.................................................................................................................................. 9

3.2.4     Nyquist Alias Zones....................................................................................................................................... 10

3.2.5     Over-Sampling and Sub-Sampling Operation....................................................................................... 11

3.2.6     Decimation, Interpolation and Processing Gain.................................................................................. 12

3.2.7     The Effect Of Sample and Hold Processes......................................................................................... 12

3.2.8     Periodic And Non Periodic Time Captured Signals........................................................................... 14

3.2.9     Data Windowing.............................................................................................................................................. 15

3.2.9.1   Simple Cosine Based Window Function..................................................................................................... 15

3.2.9.2   Applying The Window Function To Time Domain Data.......................................................................... 16

3.2.9.3   Effect Of Windowing On The Spectrum’s Dynamic Range.................................................................. 16

3.2.9.4   Effect Of Windowing On The Spectral Resolution.............................................................................. 17

3.2.10   Full Scale Input or Output.......................................................................................................................... 18

3.2.11    Aperture Based Bit Resolution................................................................................................................... 18

3.2.12   Dither.................................................................................................................................................................. 18

3.2.12.1      MATHCAD Demonstration Of The Effect Of Dither On A Quantized Signal........................ 19

3.2.13   Differential and Integral Aperture Non Linearity and Effective Bits..................................... 19

3.2.14   Clock Jitter And Its Effect On SNR..................................................................................................... 20

3.2.15   ADC Input One Port Non Linearity.......................................................................................................... 20

3.2.16   Effective ADC Noise Figure....................................................................................................................... 21

3.2.17   Effective DAC Spurious Output Energy................................................................................................ 22

3.2.18   ADC Latency..................................................................................................................................................... 23

4    Mixed Signal Device Worked Examples.............................................. 24

4.1    Receiver Worked Examples............................................................................................................................... 24

4.1.1      Medium RF Performance Mobile and Portable Sub Sampled IF ADC Application............... 24

4.1.2     High Performance Base Station Sub Sampled IF ADC Application........................................... 27

4.2   Transmitter Worked Examples..................................................................................................................... 27

4.2.1     Direct FSK IQ Based DAC Application In Analogue Direct Conversion Transmitter.......... 27

4.2.2     Cartesian Feedback RF PA Linearization Worked Example.......................................................... 27

5    Appendix.................................................................................... 28

5.1    MATHCAD Demonstration Files.................................................................................................................. 28

5.1.1      Discrete Time Sampled Waveform Demonstration............................................................................ 28

5.1.2     Quantization.................................................................................................................................................... 34

5.1.3     Symbol Error Rate Predictions For M-QAM Systems Using Normal Distribution Model... 36

5.2   Mathematical Analysis Files........................................................................................................................ 46

5.2.1     Predicting SNR Degradation On ADC Devices Caused By Clock Jitter.................................... 46

5.2.1.1    Time Domain Analysis of Clock Jitter and ADC SNR.......................................................................... 46

5.2.2     Phase Noise On A Time Sampled Sinusoid........................................................................................... 48

5.3   Associated Files................................................................................................................................................... 51

5.3.1     MATHCAD Files.............................................................................................................................................. 51

5.3.2     Component Data Files.................................................................................................................................... 51

2         Preface

2.1   Purpose of This Document

This document will discuss Mixed Signal Device (MSD) performance metrics that are relevant to RF applications. These include data acquisition devices (Analogue to Digital Converters “ADC”) and signal construction devices (Data to Analogue Converters “DAC”) suitable for RF, IF and IQ signal processing fields.

2.2   Topics Covered

This document will explain the relationship and importance of the following terms.

• Quantization, Signal Acquisition, Signal Construction
• Bit Resolution
• The Effect of Dither
• Full Scale Voltage, Current And Power
• Sample Rate F_s
• Signal to Noise Ratio (SNR)
• Signal To Noise Ratio Density in dB / 1Hz Bandwidth
• Effective MSD Noise Floor in dB / 1 Hz
• Thermal Noise Floor in dB / 1 Hz
• Effective ADC and DAC Noise Figure (NF)
• Over-sampling and Under Sampling
• Nyquist Alias Zones
• Sample and Hold
• Sinc Function Frequency Response
• Decimation and Interpolation
• ADC Noise Figure Prediction
• ADC Third Order Intermodulation Prediction
• Effect of Clock and Aperture Jitter on SNR
• SNR Degradation Mechanisms – Dynamic and Integrated Non Linearity, Jitter Noise
• Predicting Receiver Sensistivity, Selectivity and Intermodulation for ADC MSD’s.
• Predicting Transmitter Adjacent Channel Power (ACP) and Spurious Outputs for DAC’s
• Example MSD data files in embedded PDF format
• Practical Receiver Worked Examples
• Practical Transmitter Worked Examples

2.3   Exclusions

This document focuses on flash and pipe line architectures for high frequency operation. Successive Approximation ADC’s are excluded but may be used in lower frequency IQ applications below 1 MHz and often have low power requirements. Sigma Delta converters are less appropriate for high rate conversions required in RF. These devices are best left for audio signal processing and will therefore not be discussed in this document.

3        Introduction To Digital / Analogue MSD’s

3.1   Motivation For Mixed Signal Devices (MSD)

Mixed Signal Devices (MSD) combine Analogue and Digital processing elements in a single device. They are useful for signal acquisition (Analogue to Digital Conversion “ADC”) or signal generation (Digital to Analogue Conversion “DAC”) applications. As such they bridge the gap between the Analogue world and the Digital Signal Processing (DSP) world.

The Analogue world is characterised by continuous voltage and current waveforms.  In contrast, Digital systems use discrete time sampling and operate with quantized values of equivalent signal representations. Consequently, each has very different behavioural attributes that require reconciliation in each MSD.

The advantages of processing signals in the digital domain include accuracy, repeatability and flexibility. In addition, some processing algorithms can be designed that have no equivalent in the analogue domain, or, for some that may, only implementations that are clumsy, expensive and inaccurate. Although Digital signals are quantized in time and numerical value, the extent of this quantization is known and invariant, as opposed to analogue signals that are affected by variable aberrations.  These include frequency response errors, amplitude-phase non-linearity and random additive and multiplicative noise (e.g. VCO Phase Noise)

Despite the advantages of Digital Signal Processing, eventually some interaction with the outside (Analogue) world will be required. For example, speakers and headphones require analogue input signals and microphones produce analogue signal outputs. Equally, light requires analogue transducers, either as Charge Coupled Devices (CCD’s) used in cameras, or LED based computer monitor screens. Other analogue signal types include temperature transducers, motion detectors, smoke detectors and devices for chemical composition analysis. These all require an analogue signal interface, and some additional analogue signal processing, but the current industry trend is to minimise the analogue hardware overhead in favour of extended digital processing capability. The interface between these two domains can be referred to as Mixed Signal Devices (MSD) that bridge the gap between two very different worlds, so that activities in each can be optimal.

3.2   Definitions

3.2.1      Quantization

In the “real world”, quantities such as temperature, position, size, weight, etc can be considered to have infinite fine graduation in their values. However, we equally associate the value of any particular item with a cost that can only take on discrete values. European currency is counted in cents, therefore European currency is quantized in units of 1 cent. 

3.2.2      Bit Resolution

A bit resolution of 1 refers to the case where a coin, as in the previous example, is either present or not present. Its “value” is therefore 1 if present or 0 if absent. Its value “x” can therefore be represented as

…(1)

One bit converters are used for simple yes/no requirements, and in some audio applications where extreme over-sampling is used to effectively increase the number of Bits (refer to topic on decimation).

Multiple Bit MSD’s are desirable for RF applications as they provide good Bit resolution with minimum sample frequency requirements. A N-Bit value is represented as

            …(2)

For example, a 2-Bit word (N=2) has possible values of 0, 1, 2 and 3. A 3-Bit word (N=3) has values of 0, 1, 2, …  7. In other words, A N-Bit word has quantized values of 0, 1, 2, …  2^N-1.

For DC applications, The Bit value may start at 0, but RF and IQ applications usually require ± x value representations. In this situation a simple DC offset is added to the Bit-word, and equation 2 becomes,

            …(3)

This quantization can considered as a step piecewise approximation to any given quantity based on the Bit resolution N represented as a binary string  and the corresponding number of possible values (i.e. states) Q. As can be seen

…(3.5)

3.2.2.1    MATHCAD Demonstration of Signal Quantization

3.2.2.2    MATHCAD Demonstration Of Effect Of Quantization On SNR

3.2.2.3    MATHCAD Estimation Of Quantized Signal SNR in dB

3.2.3      Discrete Time Sampling

Analogue signals operate in a continuous time domain, but digital systems require that the signal is sampled at discrete time intervals. This sampling is usually performed at a constant rate referred to as the sample frequency F_s. This “snap shot by snap shot” view allows digital processing components such as Micro-processor, DSP, and FPGA’s devices to construct and analyse signals on a clock cycle by cycle basis. For perfect accuracy to be retained, F_s must be higher thane twice the bandwidth of the sampled signal.

In this example, a semi-sinusoidal signal is sampled at a low sample rate (stem plot) and a much higher sample rate (continuous plot). The captured signal value coincide for both cases, but it will be shown later that the lower sampled version will be less accurate than the higher sampled version. This is because the non-linear exponential-sin function has spectral content that extends to an indefinite frequency, but with diminishing energy content. As more of this energy is captured, the resulting accuracy improves.

3.2.4      Nyquist Alias Zones

Discrete time sampled signals have a repeating spectrum at integer multiples of ½ the sample rate F_s. Each even multiple can be described as a positive alias and each odd multiple as a negative alias.

Positive and Negative alias zones are mirror images of each other joined at a vertical line centred at , , …  where  represents the highest wanted alias frequency.

The alias zone  for + and – alias versions, given a target frequency component  and sample frequency  is therefore

            …(4)

where the function floor simply takes the lowest integer approximation to its argument .

3.2.5      Over-Sampling and Sub-Sampling Operation

The first positive Nyquist zone is often used for ADC and DAC operation. This mode is referred to as an “over-sampled” application and sampled signals usually have spectral energy components with frequencies that are significantly less than . However this zones limits a MSD’s frequency range to less than  and frequencies higher than the 1^st positive alias zone may require processing. This situation is commonplace for ADC’s which can often capture signals that can be ten times or more higher than their clock frequency. This operation is referred to as “sub sampling” and no information is lost providing the bandwidth of the signal does not exceed any given Nyquist alias zone.

The MAX1192 8 Bit ADC, for example, has a maximum clock frequency of 22 MHz, but can capture input signals as high as 400 MHz with minor performance degradation. In this example, a 400 MHz input signal would reside in the ADC’s 18^th positive alias zone, i.e. covering the frequency range of 18*22 MHz = 396 MHz to 396+22/2 = 407 MHz. 

From the previous example, we find . The 400 MHz signal, in the 18^th alias zone will be equivalent to a 4 MHz signal is the first positive alias zone. After signal acquisition, the effect of discrete time sampling makes any subsequent digital processing from being able to determine which alias zone was utilized. Consequently the 400 MHz captured input signal will be identical to a captured 4 MHz signal. Equally, a 414 MHz input signal will also produce 4 MHz as an alias, based on the ADC 18^th negative input alias response.

3.2.6      Decimation, Interpolation and Processing Gain

When people are first introduced to MSD’s they immediately assume that Bit resolution is some invariant quantity based on the number of quantization bits  and perhaps some minor imperfections in the MSD. This assumption is completely false.

Digital processing stages often use Variable Rate Processing (VRP) between successive processing stages in order to achieve more effective computational efficiency. An incoming signal may be sampled at a very high rate, and yet have very moderate signal bandwidth. It is only necessary to subsequently sample at a reduced rate based on this moderate bandwidth, after the signal has been captured (referred to as signal acquisition).

This process of down sampling is called “decimation”, and its equivalent up sampling process is called “interpolation”. In both cases, the signal’s bit resolution is altered.

Let us assume a 1 Bit ADC device (comparator) which has either a “0” or a “1” output state, operating at a sample rate of 40 MHz. Let us add, in the digital domain, each 4-group of output samples and produce a final result at the end of each 4 clock cycles. The output values will therefore occur at ¼ the incoming clock frequency, i.e. the output processed sample rate would be decimated by a factor of four.

If we add “0” and “1” output states over four captured samples, the output sums can only be,

Sums = 0, 1, 2, 3, or 4

If all captured samples had a value of 0 the sum would be zero. If all had a value of 1 then the sum would be 4. We see that we now have between 0 and 2² sates, similar to a 2 Bit word, even though the input was only a single bit. In other words, the process of decimation has caused some processing gain resulting in more bits but at a slower output sample rate.

Similarly, if we summed over 16 samples and produced an output at  the output rate, then the sum outputs would range from 0, 1, 2, … 16, i.e. 2⁴ = 16, i.e. 4 Bit resolution for this decimation by 16.

(Note: why are there always 1 extra state?)

Interpolation is a reciprocal process and results in reduced Bit resolution at a higher output sample rate. No information is either gained or lost in either process.

3.2.7      The Effect Of Sample and Hold Processes

An infinitely thin time domain repeating impulse signal has an infinite bandwidth and contains a train of repeating alias’ at multiples of its repetition rate, each of equal spectral energy. In contrast, a “staircase” pulse train has a repeating series of alias’ that fall off in a “ ” fashion. This  function is usually defined in the frequency domain as,

            …(5)

The more general Complex frequency response for a sample and hold process is,

            …(6)

The magnitude response for equation (6) is identical to that of equation (5), but an additional phase delay term is introduced from the complex exponential .

3.2.8      Periodic And Non Periodic Time Captured Signals

So far we have shown signals that are sampled at an integer multiple of repetitive (periodic) frequency. When the Fourier Transform (FT) is applied, it assumes that the total analysis time begins from Time = -¥ and ends at Time = +¥. Obviously we may not that this much time to wait. However, waveforms that repeat in the time domain can be truncated to a single repeating period, and then processed with a FT. The frequency domain Nyquist zones then also repeat with equal alias. Providing the signal bandwidth is less than ½ the sample rate frequency then no information is lost from this truncation.

However, this exact repeating periodicity can only be achieved artificially, and most signals are only approximately periodic. We will refer to these as Non-Periodic. The effect of Non-Periodicity is to cause “spectral spillage” between FT frequency Bins.

 As can be seen, a small degree on non-periodicity has drastic effects on the FT spectral interpretation. The signal itself doesn’t, just its time domain truncated FT based interpretation.

3.2.9      Data Windowing

Non-periodic signals can be converted to approximate periodic versions by applying a time domain weighting to the signal before the FT interpretation. (The computer algorithm used to perform the FT is usually referred to as a FFT, or “Fast Fourier Transform”. It is identical in performance, but just computes the spectral coefficients in an efficient manner)

There are many possible window functions, but all attempt to force the start of the time domain signal to equal the last value, usually to zero. Any function that starts at zero when t=0 and ends at zero when t=Time can be multiplied by the input time domain signal to produce a version with the same properties. This forces the new signal to look periodic. However the process changes the signal and the trade-off is between overall dynamic range and nearby frequency resolution.

The simplest Window function is based on a ½ cycle cosine function defined as,

…(7)

Here  represents the sample number starting from 0, and  represents the total number of samples (since we counted the samples from 0, rather than from 1.)

3.2.9.1    Simple Cosine Based Window Function

In general, the window function should be smooth, contain as much of the time domain signal as possible and be symmetric about its centre vertical axis. However the trade-off between amplitude dynamic range and close in frequency resolution cannot be avoided. The cosine window function covers on complete cycle, and so has a FFT Bin frequency of 1. When multiplied by the input time domain signal, adjacent “sidebands” will be generated around each spectral component. This is exactly the same situation that occurs in Amplitude Modulated (AM) systems.  Sine the depth of this AM is 100 %, each sideband will be ½ the amplitude of the wanted component (analogous to a carrier tone), which will be seen as –6 dB on a decibel scale.

The cosine window can only generate adjacent sidebands, whereas other windows will generate adjacent, alternate and higher sideband components.

3.2.9.2    Applying The Window Function To Time Domain Data

3.2.9.3    Effect Of Windowing On The Spectrum’s Dynamic Range

It might be thought that the windowing process is a bit “savage” to the wanted time domain signal, but it is merely an analysis tool that seeks to provide better spectral analysis for particular areas, usually to extend dynamic range at the expense of fine frequency resolution.

3.2.9.4    Effect Of Windowing On The Spectral Resolution

The red diamonds represent FFT Bin energy for the windowed periodic signal, and the blue squares represent FFT Bin energy for the windowed non-periodic signal. Both signals were sinusoidal with frequency of, and close to, 5 kHz over a total analysis time of 10^-3 seconds, i.e. the corresponding FFT Bin separation will be 1000 Hz.

Both signals register spectral energy of –6 dB at 5 kHz, and about –12 dB on adjacent channels, as previously explained (AM effect). However some additional spillage still occurs at FFT Bins beyond the adjacent FFT Bin spacing. This is because a signal that ends at the same place it begins is not exactly periodic. Instead the last sample point should be discarded as this would be the first sample of the next concatenated time domain block.

3.2.10  Full Scale Input or Output

All MSD’s have a maximum voltage, current or power limit, referred to as “Full Scale” or FS. Signals below FS are quantized according to a given Bit resolution. A typical ADC will have a FS input range between ± 0.5 V and ± 2.5 V. If the ADC input is terminated with a parallel resistance, then the FS input can also be interpreted in terms of maximum input power, e.g.

            …(8)

For example, if  and the parallel input termination resistance is 200 Ohms, then the maximum input power at the ADC input will be . The situation for DAC’s is similar, and both current output and voltage output versions are common.

3.2.11  Aperture Based Bit Resolution

The smallest quantized voltage step depends on FS and the Bit resolution ,

            …(9)

An eight Bit MSD with  will have  quantized levels, and its smallest voltage (or current) step will therefore be 7.8125 mV.

3.2.12  Dither

The Aperture based Bit resolution does not define the actual resolution of MSD’s used for RF applications, and is extremely pessimistic. This is because the random nature of noise allows averaging mechanisms to create the appearance of much finer resolution. As an example, consider a small signal applied to an ADC input, with a peak voltage level equal to . In this case, only one Bit will toggle based on the input signal. If the input signal is reduced, then Bit toggling would be expected to stop.

Now consider the case were a small noise voltage is added to the input signal, at a level that always ensures at least one Bit is toggling. Over a large number of samples, say 100, we would expect 50 “High” Bits and 50 “Low Bits”. As the input signal amplitude varies, then the percentages will change from 0 / 100 % through to 50 / 50 % and up to 100 / 50 % on the same toggling Bit. In other words, the ADC has captured the changing input signal with much greater resolution than its Aperture based limit would suggest.

This source of noise is called “Dither”. It has the effect of improving ADC sensitivity and to “spread out” energy that appears in some discrete spurious frequencies that may appear on the digitised output representation. High speed, high-resolution ADC ‘s tend to “self dither”, so additional noise sources are not required.  Typical 12 Bit, 40 MHz ADC’s will exhibit at least one toggling Bit, without having an external input signal applied. Lower clock rates and Bit resolution will eventually cause 1 Bit to “stick”, and then external dither is required. However, in any RF application, it is probable that amplification will be place in front of the ADC, typically 30 dB to 50 dB depending on the ADC. The noise associated with this gain is highly likely to provide adequate dither.

3.2.12.1MATHCAD Demonstration Of The Effect Of Dither On A Quantized Signal

3.2.13  Differential and Integral Aperture Non Linearity and Effective Bits

In an ideal world each quantized step would be exactly equal. However small differences in these thresholds will exist due to random variation inherent in any manufacturing process. These imperfections have the effect of reducing the Effective Number of Bits. When a MSD is operated at FS the theoretical Signal To Noise (SNR) ratio can be predicted as,

            …(10)

Measured SNR will be less, so the equivalent “effective number of Bits” is expressed as,

            …(11)

In this case, the SNR is measured over one complete Nyquist alias zone.

Differential aperture non-linearity refers to the maximum deviation between quantized amplitude steps, and should be less than 1 Bit value  for monotonic behaviour. Integral aperture non-linearity refers to the difference between any Bit step and a best-fit straight line over the ADC input amplitude range. Both these mechanisms cause a reduction in SNR and a corresponding reduction in the effective number of Bits.

3.2.14  Clock Jitter And Its Effect On SNR

All clock sources exhibit some random variation in the time between transitions. This can be expressed as an RMS average value of time, typical values of 2 ps are common for Xtal sources. The effect of this clock jitter is to place a limit on achievable SNR despite how many Bits may be available. The SNR limit depends on the frequency of the signal that is either captured (ADC) or generated (DAC)

…(12)

where  represents the frequency component in Hz that is being processed and  represents the RMS time domain jitter in seconds. For example,  implies . This is equivalent to about 10 Bit resolution. Alternatively, a 14 Bit ADC would require a clock jitter to cause a SNR deterioration less than 3 dB from theoretical. A typical 14 Bit ADC will tend to have internal jitter greater than this amount.

3.2.15  ADC Input One Port Non Linearity

High Bit resolution RF ADC devices will exhibit signal level dependant input impedance. When a signal with finite source impedance is presented to the ADC, this variable impedance causes corresponding variation in the signal’s value.

The effect of the variable ADC input impedance over its input signal trajectory can be viewed as an equivalent distortion related current injected in parallel with its input, caused by this non linearity. The resulting non linear voltage components will therefore be proportional to the total parallel impedance the ADC input “sees”.

For example, a given 12 Bit ADC may be presented as having an input inmpedance of 250 Ohms (AD9042), but if it is matched to this impedance using a 50 Ohms source, its linearity will be poor. Best 3^rd order intermodulation performance will occur if the ADC “sees” a low source impedance. For this reason, it is often a good idea to define the ADC input impedance with a parallel resistor selected to result in a 50 Ohm input (convenient also for test purposes).

3.2.16  Effective ADC Noise Figure

The ADC’s used for RF applications can be considered as RF components with an associated Noise Figure (NF) just as other RF processing devices have.

Let us assume we have an ADC with a FS input voltage range of ± with parallel input termination resistance of . The FS input power  will then be

            …(13)

The corresponding ADC input noise power , averaged over one Nyquist frequency zone will then be reduced according to the ADC’s ,

            …(14)

Since this noise is spread uniformly over each Nyquist frequency zone, the spectral noise density in a bandwidth = 1 Hz must be,

            …(15)

Since Noise Figure simply represents excess noise compared to thermal noise (at 25 C), then the ADC will have a predicted NF given by,

            …(16)

where  at 25 C. To summarise,

3.2.17  Effective DAC Spurious Output Energy

Similar analysis can be applied to DAC’s based on FS, SNR, and Noise Density. Current DAC’s tend to be somewhat more non linear than ADC’s and will exhibit a number of discrete output signals that may be much greater than expected from their Bit resolution. If a sinusoidal signal is generated, this non-linearity will result in harmonics at multiples of the sinusoidal frequency. These harmonics will then enter higher Nyquist frequency zones and “fold back” into the wanted 1^st positive alias zone. It should be noted that DAC’s, unlike ADC’s, use a sample and hold output stage and therefore exhibit a Sinc{x} frequency response. Harmonics reappearing in the wanted first positive alias zone will therefore be attenuated by this Sinc{x} response.

Note: Some recent “Tx DAC” devices (Analog Devices) are designed to also operate in the first negative alias zone. These are intended for IF signal construction, followed by Analog based frequency conversion up to higher frequencies.

Typical RF DAC’s use a constant current differential output with FS = ±10 mA or less. These may be differentially terminated with a 200 Ohm resistance intended to drive a 200 Ohm differential load. This results in a voltage swing of ±1 V into a 200 load, i.e. .

The DAC spurious output energy arises from discrete and random causes. Non-linear mechanisms, such as level dependant output compliance (output impedance variation with voltage) create harmonic energy and folds back into Nyquist zones to create non-harmonically related discrete spurious terms. These are DAC device dependant and improve when balanced outputs are used.

Spurious energy caused by random (quantization + dither) processes can be interpreted as equivalent discrete energy based on a given measurement bandwidth . The theoretical overall noise based spurious output energy for signals referenced to FS is therefore

…(17)

This equation represents a best-case estimate based on Bit resolution , Sample rate , Measurement Bandwidth  and the actual measurement centre frequency .

For example, consider a low cost 10 Bit DAC sampling at a rate of 50 MHz used for PMR transmitter applications with a measurement bandwidth of 8 kHz. A measurement frequency of 1 MHz would produce a noise based spurious output power ratio of 135.9 dB_1Hz or 96.9 dB total in the measurement bandwidth. This is significantly better than most transmitter spurious output requirements based on discrete spurious output energy. For example, a typical PMR Hand Portable will have a transmit output power of 4 Watts, or +36 dBm, and may need to comply with a spurious output power limit of –36 dBm, i.e. a ratio of 72 dB. In this example, the selected DAC would have an effective noise based spurious output ratio that would be about 25 dB better than required. The Sinc{x} sample and hold process would further improve this ratio at higher offsets, as would the effect of additional anti-alias rejection filters required, for example, on the I and Q DAC’s used in a Cartesian Feedback RF PA linearization topology.

3.2.18   ADC Latency

Unlike DAC devices, a pipeline ADC, typically used in RF applications, takes a number of clock cycles during acquisition. This typically ranges from a delay of 5 to 14 clock cycles. In some applications, such as Digital Cartesian RF PA feedback loops, the phase margin erosion caused by “Latency” requires consideration. This Latency, or clock cycle delay, generally increases as Bit resolution increases. A typical 8 Bit 50 MHz ADC will require 5 clock cycles to process an input signal, while a 12 Bit equivalent device may require 12 clock cycles.

The additional ADC phase shift  at frequency  caused from a Latency of  clock cycles can be predicted from,

            …(18)

As an example, a 12 Bit ADC clocked at 60 MHz with a Latency of 12 clock cycles will introduce a phase shift of 0.628 radians (36 degrees) for an input frequency of 500 kHz. When used in a feedback system, some phase margin loss will occur.

4        Mixed Signal Device Worked Examples

4.1   Receiver Worked Examples

4.1.1      Medium RF Performance Mobile and Portable Sub Sampled IF ADC Application

We will use the MAX1193 dual ADC as an example. This device has the following performance parameters

The MAX1193 ADC is well suited to sub sampling operation due to its high input bandwidth of 440 MHz and relatively low aperture jitter of 2 ps RMS. In fact, this low value of aperture jitter would allow input signal capture up to 299 MHz with less than 3 dB deterioration in SNR. (i.e. SNR = 48.5 dB from this mechanism alone, equal to the specified lower frequency SNR)

 We will use an IF input frequency of 45 MHz in this example, and select a clock frequency of 40 MHz. This will result in a Nyquist first positive alias of 45 – 40 = 5 MHz.

We will also need to provide a reference impedance at the ADC input in order to predict overall RF and IF gain requirements. It would not be recommended to attempt matching directly into its high input resistance of 120 kOhm at 45 MHz, as this would require very high Q matching elements and is certain to result in extremely poor linearity. The 5 pF input capacitance will represent a reactance of –j 707 Ohms at 45 MHz, so a value of 500 Ohms would probably be more realistic. We will therefore terminate the ADC input with a 560 Ohm resistor and provide a simple reactive match between this input and the previous IF gain stage.

We first need to determine the ADC Noise Figure based on this termination strategy.

The combined ADC and termination resistance will exhibit a Noise Figure of 46 dB. This provides some insight into the total IF and RF amplification requirements. For example, if a noiseless gain stage was used with 46 dB of gain, then the ADC input referred noise would be equal to thermal noise and the overall Noise Figure would therefore be 3 dB. A simple rule of thumb is to set the preceding gain equal to the difference between the ADC Noise Figure NF_ADC and the Noise Figure of the preceding combined amplification stages NF_Rx. The combined overall Noise Figure will then be 3 dB higher than NF_Rx. If less amplification is used then the ADC will dominate the overall Noise Figure. If more amplificatiion is used, the overall Noise Figure will improve slightly but ADC overload will occur earlier with increasing signal strength. The 3 dB compromise is therefore an excellent place to start initial system design.

In summary,      …(19)

We will assume a combined RF and IF Noise Figure of and that a total Noise Figure of 7 dB is acceptable. Equation 19 suggests .

We can now begin to make some predictions with respect to sensitivity and dynamic range. A receiver’s sensitivity is usually defined in terms of the input power required to achieve a given demodulated signal quality, usually expressed in terms of SINAD for Analogue FM and BER for Digital modulation Formats. These can be compared (see Appendix),

 Note: Sensitivity is predicted from

We will consider the use of Narrow Band FM which will result in a predicted sensitivity of –120 dBm. We also note that the FS input to the ADC was –6.3 dBm and that the preceding combined RF and IF gain was 42 dB. The ADC will therefore reach full scale when the received input signal exceeds –6.3 – 42 = -48.3 dBm. Relative to the predicted sensitivity limit this represents a ratio of 71.7 dB.

A typical low power hand portable receiver might only require a selectivity specification of 60 dB, based on EIA Type Approval compliance limits. The selected ADC would easily achieve this specification with a margin of 11.7 dB. However the equivalent ETS method uses a fixed input on channel level of –107 dBm. In this case the ADC will reach FS when the interfering signals exceed a ratio of 58.7 dB.

It is therefore essential to use a selectable attenuator in the preceeding gain stage, or to extend the selectivity specification by using a xtal filter. Even a wide band Xtal filter can be expected to provide >10 dB adjacent channel attenuation given a narrow band (12.5 kHz) channel offset.  

The use of such a filter will extend performance third order intermodulation immunity still further, and will help remove unwanted Nyquist alias responses.

Note: It is always good practise to remove unwanted noise that could fall into other Nyquist alias zones and therefore degrade the ADC Noise Figure performance. Usually a simple LC filter will be adequate. However, the use of a very narrow band filter (e.g. Xtal) directly at the ADC input is not recommended. This may remove beneficial broad band noise within a single Nyquist alias zone and so prevent ADC dither, causing an extreme loss of sensitivity. In ADC devices, noise is actually advantageous.

4.1.2      High Performance Base Station Sub Sampled IF ADC Application

4.2   Transmitter Worked Examples

4.2.1       Direct FSK IQ Based DAC Application In Analogue Direct Conversion Transmitter

4.2.2      Cartesian Feedback RF PA Linearization Worked Example

5        Appendix

5.1   MATHCAD Demonstration Files

5.1.1      Discrete Time Sampled Waveform Demonstration

5.1.2      Quantization

A MSD is defined in terms of Bit resolution. A “One Bit” MSD has two possible “states”, 0 or 1. A “Two Bit” MSD has 4 possible states, 0,1,2, or 3.

In this example the input value exceeds FS resulting in an output value limited to ±FS. Note the 3 Bit example has 8 possible output states ranging from –FS up to FS.

Quantization introduces uncertainty which shows up as wide band noise. Integral non linearity (deviation from a best fit straight line) introduces additional harmonic terms, and alias versions of each harmonic. Differential non linearity (variation is Quantization step size) reduces effective Bit resolution, creating additional noise.

The Quantization noise is spread evenly from DC to Fs/2. If the spectral energy terms are summed over this range, then the predicted SNR of 6.02*N+1.76 ~ 50 dB will be computed.

5.1.3      Symbol Error Rate Predictions For M-QAM Systems Using Normal Distribution Model

This model is based on a Normal Distribution associated with a random noise vector that causes symbol decision errors dependant on the noise vector’s amplitude standard deviation  and the decision threshold .

The noise vector standard deviation  is directly related to the I or Q channel noise power and the “Average Symbol Power” as follows,

For example, QAM64 has 8 Symbol Levels for channel I, and 8 Symbol Levels for channel Q. The product results in 8 * 8 = 64 combinations, hence QAM64.

It is convenient to think of each level in terms of ±1, ±3, ±5 etc. Consequently, the possible “energy levels” are 1, 9, 25 etc. Since each symbol energy level is equally probable, the average symbol energy is simply an average over all energies. Given this definition, the decision threshold is ±1, since the distant between adjacent symbols is 2.

5.2   Mathematical Analysis Files

5.2.1      Predicting SNR Degradation On ADC Devices Caused By Clock Jitter

5.2.1.1    Time Domain Analysis of Clock Jitter and ADC SNR

Consider a sinusoidal signal with voltage amplitude  and period  sampled at time  where there exists an RMS timing error of  per sample. 

The average signal power  is given by

We now want to find the average noise power resulting from this timing jitter. Over the sine-wave period  , or equivalently . From Taylor’s theorem we have

which approximates to . Consequently for each angular position  over the interval  we have

By definition  and also  so we can rewrite the previous equation as

The RMS average value of  over the sine-wave can be found by integration,

We note that the RMS average value of the perturbation voltage is equal to  that of the peak sinusoidal voltage , after integrating its contribution over the sinusoidal waveform.

It is also interesting to note that this linear relationship  implies that the spectral distributions of both are equivalent. In other words, if the time jitter spectrum is evenly distributed over frequency, then the corresponding sampled voltage spectral distribution is also equally distributed over frequency.

The associated sampled voltage noise power defined as  is then

Since this is now a power estimate, the previous  voltage scale factor  becomes . Given that  i.e.  we now have

The resulting Signal to Noise Ratio (SNR) defined in dB as  is then

Since the sinusoidal frequency  we see that

This is an interesting result and shows that SNR degrades as the RMS time jitter increases (as expected) and also as the sinusoidal input frequency increases.

5.2.2      Phase Noise On A Time Sampled Sinusoid

Many authors refer to this definition as “phase noise” and although this is mathematically correct, most people forget that phase has both real and imaginary components (i.e. it is a complex quantity). Authors referring to “phase noise” almost invariable assume its real component only, and do not address amplitude variations associated with the imaginary component of phase.

A more general description for this noise type is complex time domain jitter . This can be viewed as a multiplicative noise source with amplitude and phase perturbation terms,

Here  refers to a multiplicative noise scaling term consisting of an average gain  and with a RMS gain magnitude perturbation  and RMS gain phase perturbation  (the  symbol will be left off). In this representation  and  are both assumed to be a complex variable represented as  and , but  will be assumed to have no imaginary term for this analysis, with no loss of generality.

The term  has a Taylor series expansion given by . For small angular perturbations this complex exponential can be approximated as

Consequently

From this expression it is clear that the wanted signal and its noise contributions can be separated as,

Since  and  will both be considered as small quantities, their product will become insignificant, so we can further simplify,

Again we will define our signal as a sinusoidal function,

This has a signal power  given by,

Since this is scaled by the gain term  the output signal power  will be

Now let’s turn our attention to the noise power term. As we found previously, when integrated over a complete sinusoid, the average noise power contribution is ½ that predicted from the peak voltage term . We therefore predict that,

Since we defined  previously, the multiplicative case for SNR becomes

The phase jitter term  is related to time domain jitter  and the sinusoidal period  as

Which leads to,

And since  we can further refine the expression as

We see that this more general result is equivalent to the previous result for phase jitter noise, , when the amplitude jitter term

5.3   Associated Files

5.3.1      MATHCAD Files

5.3.2      Component Data Files