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The MOS Field Effect Transistor (MOSFET) is the fundamental building block of MOS and CMOS digital integrated circuits. Compared to the bipolar junction transistor (BJT), the CMOS occupies a relatively smaller silicon area, and its fabrication involves fewer processing steps. These technological advantages, together with the relative simplicity of MOSFET operation, have helped make the MOS transistor the most widely used switching device in LSI and VLSI circuits. The nMOS transistor is used as the primary switching device in virtually all digital circuit applications, whereas the pMOS is used mostly in conjunction with the nMOS device in CMOS circuits. However, the basic operation principles of both nMOS and pMOS transistor are very similar to each other.
The Metal Oxide Semiconductor (MOS) Structure Note that the structure consists of three layers: semiconductor (Si), called the substrate. As such, the MOS structure forms a capacitor, with the gate and the substrate acting as the two terminals (plates) and the oxide layer as the dielectric. The thickness of the silicon dioxide layer is usually between 10nm and 50nm. The carrier concentration and its local distribution within the semiconductor substrate can no be manipulated by the external voltage applied to the gate and substrate terminals.
Figure 1.0. Two terminal MOS structure
Structure and Operation of MOS Transistor (MOSFET) The basic structure of an n-channel MOSFET is shown in Fig. 1.1. This four-terminal device consists of a p-type substrate, in which two n+ diffusion regions, the drain and the source, are formed. The surface of the substrate region between the drain and the source is covered with a thin oxide layer, and the metal (or polysilicon) gate is deposited on top of this gate dielectric. The two n+ regions will be the current-conducting terminals of this device. Note that the device structure is completely symmetrical with respect to the drain and source regions; the different roles of these two regions will be defined only in conjunction with the applied terminal voltages and the direction of the current
flow.
Figure 1.1 The physical structure of an n-channel enhancement-type MOSFET A conducting channel will eventually be formed through applied gate voltage in the section of the device between the drain and the source diffusion regions. The distance between drain and the source diffusion regions is the channel length L, and the lateral extent of the channel (perpendicular to the length dimension) is the channel width W . Both the channel length and width are important parameters which can be used to control some of the electrical properties of the MOSFET. The thickness of the oxide layer covering the channel region, tox, is also an important parameter. A MOS transistor which has no conducting channel region at zero gate bias is called an enhancement-type (or enhancement mode) MOSFET. If a conducting channel already exists at zero gate bias, the device is called a depletion-type (or depletion mode) MOSFET. In a MOSFET with p-type substrate and with n+ source and drain regions, the channel region to be formed on the surface is n-type. Thus, such a device with p-type substrate is called an n-channel MOSFET. In a MOSFET with n-type substrate and with p+ source and drain regions, on the other hand, the channel is p-type and the device is called p-channel MOSFET.
n-channel MOSFET
p-channel MOSFET Figure 1.2. Circuit symbols for n-channel and p-channel enhancement-type MOSFETs
The abbreviations used for the device terminals are: G for the gate, D for the drain, s for the source, and B for the substrate (or body). In an n-channel MOSFET, the source is defined as the n+ region which has a lower potential than the other n+ region, the drain. By conventional, all terminal voltages of the device are defined with respect to the source potential. Thus, the gate-to-source voltage is denoted by VGS, the drain-to-source voltage is denoted by VDS, and the substrate-to-source voltage is denoted by VBS. Circuit symbols for both n-channel and p-channel enhancement type is shown in Fig. 1.2.
Figure 1.3. Formation of a depletion region in an n-channel enhancement- type MOSFET MOSFET Operation: A Qualitative View The basic structure of the n-channel MOS (nMOS) transistor built on a p-type substrate was shown in Fig.1.4. The MOSFET consists of a MOS capacitor with two p-n junctions placed immediately adjacent to the channel region that is controlled by the MOS gate. The carrier, i.e., electrons in an nMOS transistor, enter the structure through the source contact (S), leave through the drain (D), and are subject to the control of the gate (G) voltage. To ensure that both p-n junctions are reversed-biased initially, the substrate potential is kept lower than the other three terminal potentials. We have seen that when 0<VGS<VTO, the gated region between the source and the drain is depleted; no carrier flow can be observed in the channel. As the gate voltage is increased beyond the threshold voltage (VGS<VTO), however, the mid-gap energy level at the surface is pulled below the Fermi level, causing the surface potential Øs to turn positive and to invert the surface (Fig.1.4(a)). Once the inversion layer is established on the surface, an n-type conducting channel forms between the source and the drain, which is capable of carrying the drain current. Next, the influence of drain-to-source bias VDS and different modes of drain current flow will be examined for an nMOS transistor with VGS>VTO. At VDS = 0, thermal equilibrium exists in the inverted channel region, and the drain current ID is equal to zero (Fig.1.4(B) ). If a small drain voltage VDS>0 is applied, a drain current proportional to VDS will flow from the source to the drain through the conducting channel. The inversion layer, i.e., the channel, forms a continuous current path from the source to the drain. This operation mode is called the linear mode or the linear region. Thus, in linear region operation, the channel region acts as a voltage-controlled resistor. The electron velocity in the channel for this case is usually much lower than the drift velocity limit. Note that as the drain voltage is increased, the inversion layer charge and the channel depth at the drain end start to decrease. Eventually, for VDS = VDSAT, the inversion charge at the drain is reduced to zero, which is called the pinch-off point(Fig.1.4(c)).
(a)
(b)
(c) Figure 1.4 Cross-sectional view of an nchannel(nMOS) transistor, (a) operating in the linear region, (b) operating at the edge of saturation, and (c) operating beyond saturation
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