RE: [PROTEL EDA USERS]: Multiple GND nets and I want no plane connection for one of them...

[Abd ul-Rahman Lomax <marjan@vom.com>]

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At 11:04 PM 9/10/00 -0400, D. Chris Mackensen wrote:

> > This is a part having a footprint with two pads (or more) which are
> > separated from each other in the PCB database by perhaps .004 mil. Yes, 4
> > micro-inches.
>
>yes, I have seen this now that I recall.... It was actually on an allegro
>board where sense lines had to be run separately from a DCDC converter (same
>concept)...  I think the new PE14 version of allegro will have this feature
>native without faking it.  But given the huge price for allegro (and its
>complexity and general unautomated pain to use) I think I'll stick with
>Protel for my projects here at home...

All Protel needs is one of two things to be able to handle these shorting 
components without "faking" it:

(1) A design rule that allows the pads of a named component to short to 
each other even if they have different nets. To get a little nicer, each 
pad in that component could be shorted or otherwise too close to any 
primitive with a net connected to any other pad of the component. (As to 
why this would be desireable, it makes it simpler to implement these 
shorts; the pads could even superimpose on each other and could be small; 
thus the location of the common ground point would be easily controllable 
without worrying about primitives getting too close to the *other* pads on 
the part. That this is not true now requires a shorting footprint need some 
care. This is no great problem, since any mistake made with this will 
simply create a DRC error, but why not make it easy?)

(2) The DRC exception rule, analogous to a no-ERC directive in schematic. 
This would be helpful in many ways, but it is less than completely obvious 
how to implement it. There are many possible ways; it's not as simple as 
with schematic, where error markers have a known and single location. But 
DRC errors generate a characteristic message, and the no-DRC rule could 
match proposed errors to a list of no-DRC messages; if there was a match, 
the error would be suppressed. This is relatively safe because, as with 
other design rules, it would be self-documenting.

Accel PCAD has "Copper Ties," which essentially are polygons with more than 
one net assigned to them. This is reasonable from the PCB side of things, 
but I think that even our workaround methods are better because, if I am 
correct, the PCAD Copper Ties are not schematic-controlled, but are 
manually placed on the PCB. Our workaround is very well controlled from the 
schematic. You won't forget to do it, if the schematic is correct. All you 
have to do is make a footprint that works, and place a jumper on the 
schematic which is assigned this footprint. Set it and forget it; if you 
make a mistake on the PCB, DRC will tell you.

(Note that our "fake" shorts are probably robust, that is, they should 
continue to work through future revisions and technology advances, for a 
long time. It'll be a while before we are plotting PCB films with a 
resolution of .005 mils. Right now, you have to pay quite a bit extra, I 
understand, for .1 mil.... And if one is going to use a totally new 
technology for making boards, other than etched copper, that could handle 
...005 mil copper gaps, our existing copper designs probably need quite a bit 
of review anyway. And if, by some miracle, an actual gap did come to be 
fabricated, it would certainly not survive soldering, and if some new 
connection technology were being used, it should be easy to short out pads 
which are so close to each other....)

marjan@vom.com
Abdulrahman Lomax
P.O. Box 690
El Verano, CA 95433



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