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Evolving a Super
Computing Architecture for modelling the Cortex: Towards
Understanding Color Information Encoding (Individual
Thesis Work at WARF) Advisor: Prof.N.Venkateswaran
Abstract
This thesis aims at deciphering the spatio temporal color information encoding
taking place along the visual pathway. The approach adopted is dominant
frequency analysis of the cell response on a per layer basis. This work also
involves the development of a Super Computing architecture for modelling the
cortex. This architecture will help study the effect of synaptic dynamics on the
information encoding process. This is a part of a major research project ROCin BRAIN done
at WARF.
Expected
Completion Date : March 2004
 THESIS
PROPOSAL INTERIM
REPORT
KDSP1010: A LOW
POWER DSP ARCHITECTURE DESIGN
Abstract
Digital
signal processing, image processing and cryptography
involve a variety of algorithms such as convolution,
correlation, matrix operations, polynomial arithmetic
and transforms. These algorithms are characterized by
intense com-putation, matrix appearance and local data
communication and high frequency of multiplication &
addition operations. Ultra high performance architectures
can be designed and implemented for the execution of
these algorithms in DSP applications, using multi giga
hertz Deep Submicron (DSM) technology. The device count
in such architectures is of the order of several hundred
millions. Achieving low power for such an architecture
without compromising on performance is a challenge.
This
project presents the design of a power aware high speed
DSP architecture - KDSP1010. K in KDSP1010 stands
for cool(Kool) emphasizing the low power nature of the
proposed architecture. 1010 is the initial version of
the processor. We plan to enhance the design and come
out with advanced DSP series architecture. KDSP1010
is endowed with special purpose high speed 16 operand
MOA (Multiple Operand Adder) & CM4*
which is a four operand high performance floating point
chain multiplier that can cater upto 80 bit operands.
f4add, a four operand floating point high speed
adder is the basic functional unit in the proposed design
of MOA CM4*. All the aforesaid functional units have
been described using hardware descriptor languages and
c language. The simulation results are presented here.
Certain DSP transforms (Fast Fourier Transforms) are
mapped on DSP1010 and the results enunciate the
power of the proposed architecture.
Techniques
for designing low power architectures include ad hoc
designs, reduced memory access techniques or variable
power supply corresponding to the workload (present
in the current computation cycle) The power saving
techniques proposed concerns only with the dynamic power.
Bypassing of functional units when the computation involves
either 1 or 0 is an technique adopted to reduce the
dynamic power here. Functional units that remain inactive
for several cycles during the execution of a DSP algorithm
consume enormous amount of static power. In DSM technology
(90nm and below) the static power consumed due to leakage
current is around 30-35One way of reducing the static
power is by employing temporary shutdown of inactive
nodes. The various techniques are dealt with here.
Project
Completed on : October 2003 Duration: 2 months
PROJECT
REPORT
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